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1.
Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA's
by Pathanjali, Nandini, M.S.  University of Cincinnati. 2002: 110 pages; 10857176.
2.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
3.
Reliability-Aware Placement and Routing for FPGAs
by Abdul-Aziz, Mohammed A., M.S.  Northeastern University. 2010: 94 pages; 1489294.
4.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
5.
Reconfigurable computing: Power consumption optimization in embedded systems
by Varadarajan, Srihari, M.S.  California State University, Long Beach. 2014: 78 pages; 1569997.
6.
Comparative Analysis of Space-Grade Processors
by Lovelly, Tyler Michael, Ph.D.  University of Florida. 2017: 85 pages; 13847472.
7.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
8.
Acceleration of Compute-Intensive Applications on Field Programmable Gate Arrays
by Rodríguez Borbón, Jose Milet , Ph.D.  University of California, Riverside. 2020: 161 pages; 27742586.
10.
Reliability-Aware CAD Tools for SRAM-Based FPGAs
by Golshan, Shahin, Ph.D.  University of California, Irvine. 2011: 148 pages; 3481525.
11.
Application hardware-software co-design for reconfigurable computing systems
by Saha, Proshanta, Ph.D.  The George Washington University. 2008: 151 pages; 3297468.
13.
Toward hardware-oriented defensive network infrastructure
by Chen, Hao, Ph.D.  State University of New York at Binghamton. 2015: 194 pages; 3713553.
14.
Fast modular exponentiation using residue domain representation: A hardware implementation and analysis
by Nguyen, Christopher Dinh, M.S.  University of Maryland, Baltimore County. 2013: 129 pages; 1551346.
15.
Integrated hardware/software approaches to software security for embedded systems
by Gelbart, Olga, D.Sc.  The George Washington University. 2008: 137 pages; 3297440.
16.
Hardware acceleration of database applications
by Moussalli, Roger, Ph.D.  University of California, Riverside. 2013: 193 pages; 3559997.
18.
Hardware Support for Productive Partitioned Global Address Space (PGAS) Programming
by Serres, Olivier, Ph.D.  The George Washington University. 2016: 122 pages; 3746724.
19.
NodeBlaze: Using reprogrammable logic to advance sensor networking technology
by Gruenwald, Charles, M.S.  University of Colorado at Boulder. 2007: 57 pages; 1447677.
20.
Design and Verification of a DFI-AXI DDR4 Memory PHY Bridge Suitable for FPGA Based RTL Emulation and Prototyping
by Mayekar, Pallavi Avinash, M.S.  Rochester Institute of Technology. 2019: 122 pages; 22615759.
21.
Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S.  California State University, Long Beach. 2016: 80 pages; 10196051.
22.
Digital feedback control of MEMS devices: Design challenges and power efficient design using multi-timescales
by Kataria, Nitin, Ph.D.  University of California, Santa Barbara. 2009: 189 pages; 3371652.
23.
Smart Real-time Image Processing for Ultrasounds Using Cellular Neural Network
by Ayoubi, Randa, Ph.D.  University of Louisiana at Lafayette. 2014: 123 pages; 3711169.
25.
Duck Hunt FPGA game, a project on UML and digital design
by Nguyen, Vuong D., M.S.  California State University, Long Beach. 2016: 65 pages; 10137441.
26.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
27.
Power control architectures for cold cathode fluorescent lamp and light emitting diode based light sources
by Doshi, Montu V., Ph.D.  University of Colorado at Boulder. 2010: 220 pages; 3404046.
28.
A Hardware-in-the-Loop Platform for DC Protection
by Vygoder, Mark, M.S.  The University of Wisconsin - Milwaukee. 2020: 109 pages; 27961677.
29.
FPGA implementation of self testing USART
by Rana, Vireshsingh, M.S./M.P.H.  California State University, Long Beach. 2016: 37 pages; 10141518.
30.
Implementation of UART with BIST technique in FPGA
by Pradhan, Suyash, M.S.  California State University, Long Beach. 2016: 50 pages; 10111201.
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