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1.
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler
by Lee, Yunsup, Ph.D.  University of California, Berkeley. 2016: 157 pages; 10151006.
2.
Enabling dynamic voltage and frequency scaling in multicore architectures
by Prasad, Amithash, M.S.  University of Colorado at Boulder. 2009: 74 pages; 1473683.
4.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
5.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
6.
Filtered bank associative TLB with victim buffering for reduced access to main TLB and power optimization
by Castle, Michael, M.S.  California State University, Long Beach. 2011: 108 pages; 1499238.
7.
A parallel implementation of Gibbs sampling algorithm for 2PNO IRT models
by Rahimi, Mona, M.S.  Southern Illinois University at Carbondale. 2011: 72 pages; 1500979.
8.
A Vector Parallel Branch and Bound Algorithm
by Guilbeau, Jared T., Ph.D.  University of Louisiana at Lafayette. 2016: 100 pages; 10242153.
9.
Provably Efficient Algorithms for Numerical Tensor Algebra
by Solomonik, Edgar, Ph.D.  University of California, Berkeley. 2014: 256 pages; 3686016.
10.
Autonomous 3D Model Generation of Orbital Debris using Point Cloud Sensors
by Trowbridge, Michael Aaron, M.S.  University of Colorado at Boulder. 2014: 115 pages; 1558774.
11.
Heterogeneous construction of spatial data structures
by Butts, Robert O., M.S.  University of Colorado at Denver. 2015: 65 pages; 1588178.
12.
A control-theoretic design and analysis framework for resilient hard real-time systems
by Hettiarachchi, Pradeep M., Ph.D.  Wayne State University. 2015: 167 pages; 3723517.
13.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
15.
Advanced bit manipulation instructions: Architecture, implementation and applications
by Hilewitz, Yedidya, Ph.D.  Princeton University. 2008: 232 pages; 3332424.
16.
Queue Streaming Model: Theory, Algorithms, and Implementation
by Zope, Anup D., Ph.D.  Mississippi State University. 2019: 215 pages; 13860290.
17.
Simulation and characterization of inter-process interference on multithreaded and multicore architectures
by Kihm, Joshua Lee, Ph.D.  University of Colorado at Boulder. 2008: 309 pages; 3315818.
18.
Locating an Autonomous Car Using the Kalman Filter to Reduce Noise
by Hema Balaji, Nagarathna, M.S.  California State University, Long Beach. 2018: 62 pages; 10978429.
19.
The Immersed Interface Method for Flow Around Non-Smooth Boundaries and Its Parallelization
by Liu, Yang, Ph.D.  Southern Methodist University. 2017: 135 pages; 10283304.
20.
In-Node, Low Power Vehicle Classification and Identification System
by Shuck, Timothy A., M.S.  California State University, Long Beach. 2018: 58 pages; 10978575.
21.
Dissertation beyond shared memory loop parallelism in the polyhedral model
by Yuki, Tomofumi, Ph.D.  Colorado State University. 2013: 137 pages; 3565471.
22.
Hardware Support for Productive Partitioned Global Address Space (PGAS) Programming
by Serres, Olivier, Ph.D.  The George Washington University. 2016: 122 pages; 3746724.
23.
Architectures for secure cloud computing servers
by Szefer, Jakub M., Ph.D.  Princeton University. 2013: 355 pages; 3597568.
24.
Efficient ray tracing architectures
by Spjut, Josef Bo, Ph.D.  The University of Utah. 2015: 129 pages; 3727095.
25.
Analysis and Detection of the Silent Thieves
by Perez, Jon, M.S.  Utica College. 2018: 94 pages; 10931156.
26.
Topics in communication avoiding algorithms and stability analysis
by Lowery, Bradley R., Ph.D.  University of Colorado at Denver. 2014: 136 pages; 3621837.
27.
Investigations into Parallelizing Rank-One Tensor Decompositions
by Morgan, William Russell, IV, M.S.  University of Maryland, Baltimore County. 2017: 78 pages; 10683240.
28.
FPGA implementation of Rajendra Kumar's adaptive receiver for higher order modulated signal over fading channel
by Bhagavatula, Falgun, M.S.  California State University, Long Beach. 2016: 44 pages; 10142980.
29.
Design for Competitive Automated Layout (DCAL) of Superscalar Processors
by Ku, Sungkwan, Ph.D.  North Carolina State University. 2017: 106 pages; 10970028.
30.
Hardware Transactional Memory: A Systems Perspective
by Rossbach, Christopher John, Ph.D.  The University of Texas at Austin. 2009: 204 pages; 3434949.
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