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61.
On-chip demonstration of carbon nanotube interconnects
by Close, Gael F., Ph.D.  Stanford University. 2008: 134 pages; 3313812.
63.
A control framework for continuous time adaptation in modern day embedded systems
by Kallakuri, Sankalp, Ph.D.  State University of New York at Stony Brook. 2007: 147 pages; 3334943.
64.
Zinc Cadmium Selenide Cladded Quantum Dot Based Electroluminescent and Nonvolatile Memory Devices
by Al-Amody, Fuad H., Ph.D.  University of Connecticut. 2011: 144 pages; 3485263.
65.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
66.
Thermal analysis for nanometer-scale integrated circuits
by Hassan, Zyad, M.S.  University of Colorado at Boulder. 2009: 98 pages; 1473684.
67.
Collective Pulse Dynamics: A New Timing Circuit Strategy
by Dalakoti, Aditya, Ph.D.  University of California, Santa Barbara. 2018: 138 pages; 10932913.
68.
Digital feedback control of MEMS devices: Design challenges and power efficient design using multi-timescales
by Kataria, Nitin, Ph.D.  University of California, Santa Barbara. 2009: 189 pages; 3371652.
69.
Software modulated fault tolerance
by Reis, George A., III, Ph.D.  Princeton University. 2008: 104 pages; 3308327.
70.
Reliable SRAM Fingerprinting
by Kim, Joonsoo, Ph.D.  The University of Texas at Austin. 2011: 175 pages; 3572874.
71.
Side channel attack resistance: Migrating towards high level methods
by Borowczak, Mike, Ph.D.  University of Cincinnati. 2013: 183 pages; 3601397.
72.
A Die-level Adaptive Test Scheme for Real-time Test Reordering and Elimination
by Gotkhindikar, Kapil Ramesh, M.S.  Portland State University. 2012: 64 pages; 1515828.
73.
Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S.  California State University, Long Beach. 2016: 80 pages; 10196051.
74.
Low voltage switched-current cell and its application
by Holmstedt, Carol, M.S.  California State University, Long Beach. 2013: 48 pages; 1523053.
75.
Smart Real-time Image Processing for Ultrasounds Using Cellular Neural Network
by Ayoubi, Randa, Ph.D.  University of Louisiana at Lafayette. 2014: 123 pages; 3711169.
76.
Traffic pattern in negatively curved network
by Lou, Mingji, Ph.D.  University of Southern California. 2008: 124 pages; 3341712.
79.
Chip-Scale Fluorescence Microscope
by Papageorgiou, Efthymios Philip, Ph.D.  University of California, Berkeley. 2019: 84 pages; 13883892.
80.
SRAM reliability improvement using ECC and circuit techniques
by McCartney, Mark P., Ph.D.  Carnegie Mellon University. 2014: 131 pages; 3733956.
82.
Design of Multi-Gb/s Multi-Coefficient Mixed-Signal Equalizers
by Thakkar, Chintan S., Ph.D.  University of California, Berkeley. 2012: 127 pages; 3686464.
83.
A Scalable, High Sensitivity CMOS Electric Field Sensor
by Schaub, R. M., M.S.  State University of New York at Buffalo. 2012: 108 pages; 1520015.
84.
Carrier transport in dirac-band materials and their device physics
by Gupta, Gaurav, Ph.D.  National University of Singapore (Singapore). 2015: 239 pages; 10006002.
85.
Design of aging-aware variable-latency multiplier based on adaptive hold logic
by Pabbati Reddy, Sreeram Reddy, M.S.  California State University, Long Beach. 2016: 50 pages; 1606098.
86.
Physical planning to embrace interconnect dominance in power and performance
by Wang, Renshen, Ph.D.  University of California, San Diego. 2010: 60 pages; 3404703.
87.
Filtered bank associative TLB with victim buffering for reduced access to main TLB and power optimization
by Castle, Michael, M.S.  California State University, Long Beach. 2011: 108 pages; 1499238.
89.
Ultra reliable computing systems
by Lee, Chong Ho, Ph.D.  Portland State University. 2007: 224 pages; 3294668.
90.
Formal Modeling and Verification of Delay-Insensitive Circuits
by Park, Hoon, Ph.D.  Portland State University. 2015: 187 pages; 3743768.
61 - 90 of 307 displayed.
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