Results

Looking for more? ProQuest® Dissertations & Theses has additional dissertations and theses.
311 open access dissertations and theses found for:
if(VLSI)  »   Refine Search
1.
Early Prediction of Epilepsy Seizure via VLSI BCI Based System
by ElSayed, Zaghloul, Ph.D.  University of Louisiana at Lafayette. 2016: 174 pages; 10163299.
2.
Architectures for cryptography accelerators
by Cohen, Aaron Ethan, Ph.D.  University of Minnesota. 2007: 199 pages; 3277590.
3.
Developing a neural prosthesis for hippocampus: Proof-of-concept using the in vitro slice
by Hsiao, Min-Chi, Ph.D.  University of Southern California. 2009: 79 pages; 3355409.
4.
New tests and test methodologies for scan cell internal faults
by Yang, Fan, Ph.D.  The University of Iowa. 2009: 155 pages; 3390232.
5.
Quadratic and linear optimization with analog circuits
by Vichik, Sergey, Ph.D.  University of California, Berkeley. 2015: 135 pages; 10086165.
6.
7.
Duty-Cycle Based Physical Unclonable Functions (PUFs) for Hardware Security Applications
by Azhar, Mahmood Javed, Ph.D.  University of South Florida. 2018: 100 pages; 10980455.
8.
FPGA implementation of self testing USART
by Rana, Vireshsingh, M.S./M.P.H.  California State University, Long Beach. 2016: 37 pages; 10141518.
9.
Design considerations for high-speed backplane transceivers with digital adaptive equalizers
by Chung, Hayun Cecillia, Ph.D.  Harvard University. 2009: 125 pages; 3385565.
10.
Design Considerations for Nano-Electromechanical Relay Circuits
by Spencer, Matthew Edmund, Ph.D.  University of California, Berkeley. 2015: 102 pages; 3733438.
11.
Design For Test for OSU Standard Cell Library Used at GWU
by Gibb, William, M.S.  The George Washington University. 2014: 74 pages; 1560525.
12.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
13.
Implementation of UART with BIST technique in FPGA
by Pradhan, Suyash, M.S.  California State University, Long Beach. 2016: 50 pages; 10111201.
14.
Design Automation for Carbon Nanotube Circuits Considering Performance and Security Optimization
by Liu, Lin, Ph.D.  Michigan Technological University. 2017: 169 pages; 10267186.
15.
III-V and 2D Devices: From MOSFETs to Steep-Slope Transistors
by Si, Mengwei, Ph.D.  Purdue University. 2018: 148 pages; 10838712.
16.
Investigating Accuracy of the Reconfigurable Optical Computer (ROC) in Metatronics for Solving Partial Differential Equations
by Crandall, Joseph Warren, M.S.  The George Washington University. 2019: 82 pages; 13864207.
17.
High-speed carry skip adder implemented using speculative Han-Carlson parallel prefix adder
by Narayanaswamy, Rakesh, M.S.  California State University, Long Beach. 2016: 45 pages; 10007410.
18.
Reduction of energy consumption on Network-On-Chip using a data encoding technique
by Gadde, Virinchi, M.S.  California State University, Long Beach. 2016: 43 pages; 10099873.
20.
Reverse converter design based on the New Chinese Remainder Theorem II using parallel prefix adders
by Sidda, Aditya, M.S.  California State University, Long Beach. 2016: 76 pages; 10182140.
21.
FinFET memory cell improvements for higher immunity against single event upsets
by Sajit, Ahmed Sattar, M.S.  California State University, Fullerton. 2016: 63 pages; 10244875.
22.
Improvement of a propagation delay model for CMOS digital logic circuits
by Stamness, Rodger Lawrence, M.S.  San Jose State University. 2010: 100 pages; 1477363.
23.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
24.
Performance enhancement of a multiprecision multiplier by a dynamic voltage scaling and multiprecision operands scheduling
by Bugata Venkata Phani Srirama, Kalyan Chakravarthy, M.S.  California State University, Long Beach. 2016: 38 pages; 10111181.
25.
Dynamic Load-Based Power and Clock Gating Techniques for High-Speed Digital Circuits
by Farah, Salim, Ph.D.  University of Louisiana at Lafayette. 2014: 128 pages; 3622218.
26.
Incorporating the effect of delay variability in path based delay testing
by Tayade, Rajeshwary G., Ph.D.  The University of Texas at Austin. 2009: 180 pages; 3371817.
27.
28.
System level methodology for low cost performance characterization of analog and mixed -signal circuits
by Park, Joon Sung, Ph.D.  The University of Texas at Austin. 2009: 149 pages; 3372676.
29.
Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate
by Midde, Bharath Reddy, M.S.  California State University, Long Beach. 2016: 59 pages; 10099864.
30.
Design techniques for ultra-low-voltage and ultra-low-power pipelined ADCs
by Shen, Junhua, Ph.D.  Columbia University. 2010: 157 pages; 3420870.
1 - 30 of 311 displayed.
  1    2    3    4    5    6    7    8    9    10   Next >
Copyright © 2019 ProQuest LLC. All rights reserved. Terms and Conditions Privacy Policy Cookie Policy
ProQuest