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1.
Reliable SRAM Fingerprinting
by Kim, Joonsoo, Ph.D.  The University of Texas at Austin. 2011: 175 pages; 3572874.
2.
Performance evaluation of 64 bit SRAM and DRAM
by Kaushal, Kavit, M.S.  California State University, Long Beach. 2017: 72 pages; 10260954.
3.
FinFET memory cell improvements for higher immunity against single event upsets
by Sajit, Ahmed Sattar, M.S.  California State University, Fullerton. 2016: 63 pages; 10244875.
4.
Architecting emerging memory technologies for energy-efficient computing in modern processors
by Jianxing, Wang, Ph.D.  National University of Singapore (Singapore). 2015: 161 pages; 10006096.
5.
Multi-Port Automation for SRAM Compiler Design
by Grimes, Michael T., M.S.  University of California, Santa Cruz. 2018: 42 pages; 13423318.
6.
Reliability-Aware CAD Tools for SRAM-Based FPGAs
by Golshan, Shahin, Ph.D.  University of California, Irvine. 2011: 148 pages; 3481525.
7.
SRAM reliability improvement using ECC and circuit techniques
by McCartney, Mark P., Ph.D.  Carnegie Mellon University. 2014: 131 pages; 3733956.
8.
Design for Competitive Automated Layout (DCAL) of Superscalar Processors
by Ku, Sungkwan, Ph.D.  North Carolina State University. 2017: 106 pages; 10970028.
9.
Types for the Chain of Trust: No (Loader) Write Left Behind
by Shapiro, Rebecca, Ph.D.  Dartmouth College. 2018: 221 pages; 10811531.
10.
Reliability-Aware Placement and Routing for FPGAs
by Abdul-Aziz, Mohammed A., M.S.  Northeastern University. 2010: 94 pages; 1489294.
11.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
12.
Design Considerations for Nano-Electromechanical Relay Circuits
by Spencer, Matthew Edmund, Ph.D.  University of California, Berkeley. 2015: 102 pages; 3733438.
13.
Application hardware-software co-design for reconfigurable computing systems
by Saha, Proshanta, Ph.D.  The George Washington University. 2008: 151 pages; 3297468.
14.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
15.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
16.
Filtered bank associative TLB with victim buffering for reduced access to main TLB and power optimization
by Castle, Michael, M.S.  California State University, Long Beach. 2011: 108 pages; 1499238.
17.
Self-Timed Circuits, Memories, and Power Electronics for High-Ripple Energy Harvesting Power Supplies
by Wenck, Justin A., Ph.D.  University of California, Davis. 2010: 258 pages; 3427486.
18.
Early Prediction of Epilepsy Seizure via VLSI BCI Based System
by ElSayed, Zaghloul, Ph.D.  University of Louisiana at Lafayette. 2016: 174 pages; 10163299.
19.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
20.
Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S.  California State University, Long Beach. 2016: 80 pages; 10196051.
21.
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler
by Lee, Yunsup, Ph.D.  University of California, Berkeley. 2016: 157 pages; 10151006.
22.
Smart Writing of Programmable Metallization Cell
by Raval, Rizu, M.S.  California State University, Long Beach. 2018: 71 pages; 10786883.
25.
Ultra reliable computing systems
by Lee, Chong Ho, Ph.D.  Portland State University. 2007: 224 pages; 3294668.
26.
An optimized modified booth recoder for efficient design of the add-multiply operator
by Mehta, Kunal, M.S.  California State University, Long Beach. 2015: 35 pages; 1603343.
27.
Abstractions and algorithms for control of extensible and heterogeneous virtualized network infrastructures
by Wiseman, Charles Gordon, Ph.D.  Washington University in St. Louis. 2010: 205 pages; 3412319.
28.
29.
Power and thermal modeling for the proto-VIPRAM chip
by Xia, Wenbo, M.S.  Southern Methodist University. 2014: 113 pages; 1569659.
30.
Improvement of a propagation delay model for CMOS digital logic circuits
by Stamness, Rodger Lawrence, M.S.  San Jose State University. 2010: 100 pages; 1477363.
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