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1.
Design techniques for ultra-low-voltage and ultra-low-power pipelined ADCs
by Shen, Junhua, Ph.D.  Columbia University. 2010: 157 pages; 3420870.
2.
Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA's
by Pathanjali, Nandini, M.S.  University of Cincinnati. 2002: 110 pages; 10857176.
5.
Real-time solid voxelization using multi-core pipelining
by Liao, Duoduo, Ph.D.  The George Washington University. 2009: 191 pages; 3344878.
6.
Heterogeneous construction of spatial data structures
by Butts, Robert O., M.S.  University of Colorado at Denver. 2015: 65 pages; 1588178.
7.
Algorithms and hardware designs for decimal multiplication
by Erle, Mark A., Ph.D.  Lehigh University. 2009: 229 pages; 3344791.
8.
Toward a software pipelining framework for many-core chips
by Ributzka, Juergen, M.S.  University of Delaware. 2009: 97 pages; 1469538.
9.
A special unit to speed up a DSP processor
by Chenna Subbanagari, Uday Kumar Reddy, M.S.  California State University, Long Beach. 2016: 50 pages; 10108176.
10.
Complexity and power consumption in stochastic iterative decoders
by Payak, Keyur M., M.S.  Utah State University. 2010: 52 pages; 1483787.
11.
The Hybrid Task Graph Scheduler
by Blattner, Timothy, Ph.D.  University of Maryland, Baltimore County. 2016: 152 pages; 10245475.
12.
Auxiliary Roles in STT-MRAM Memory
by Das, Jayita, Ph.D.  University of South Florida. 2014: 122 pages; 3666526.
13.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
14.
Performance enhancement of a multiprecision multiplier by a dynamic voltage scaling and multiprecision operands scheduling
by Bugata Venkata Phani Srirama, Kalyan Chakravarthy, M.S.  California State University, Long Beach. 2016: 38 pages; 10111181.
15.
Investigation into the feasibility of shadow generation on mobile graphic cards
by Kiguta, NIcholas Maina, M.S.  The University of Iowa. 2010: 68 pages; 1488277.
16.
Tideflow: A dataflow-inspired execution model for high performance computing programs
by Orozco, Daniel A., Ph.D.  University of Delaware. 2012: 163 pages; 3527015.
17.
Hardware acceleration of database applications
by Moussalli, Roger, Ph.D.  University of California, Riverside. 2013: 193 pages; 3559997.
18.
Design and architecture of automatically-generated energy-reducing coprocessors
by Sampson, John Morgan, Ph.D.  University of California, San Diego. 2010: 119 pages; 3422889.
19.
Methods for performance optimization of latency-insensitive systems
by Li, Cheng-Hong, Ph.D.  Columbia University. 2010: 214 pages; 3401048.
20.
Low Complexity Sub-Nyquist Spectrum Sensing for Wideband Cognitive Radios
by Shaban, Mohamed, Ph.D.  University of Louisiana at Lafayette. 2016: 116 pages; 10003781.
22.
Architectures for cryptography accelerators
by Cohen, Aaron Ethan, Ph.D.  University of Minnesota. 2007: 199 pages; 3277590.
23.
Use of GPU architecture to optimize Rabin fingerprint data chunking algorithm by concurrent programming
by Wang, Sean, M.S.  California State University, Long Beach. 2016: 48 pages; 10108186.
24.
Robust and efficient inference of scene and object motion in multi-camera systems
by Sankaranarayanan, Aswin C., Ph.D.  University of Maryland, College Park. 2009: 181 pages; 3391385.
25.
Identifying and Resolving Entities in Text
by Durrett, Gregory Christopher, Ph.D.  University of California, Berkeley. 2016: 93 pages; 10192292.
28.
Opportunities for near data computing in MapReduce workloads
by Pugsley, Seth Hintze, Ph.D.  The University of Utah. 2015: 98 pages; 3704952.
29.
Specification and Optimization of Analytical Data Flows
by Hüske, Fabian, Ph.D.  Technische Universitaet Berlin (Germany). 2016: 210 pages; 27610212.
30.
Network Abstractions for Designing Reliable Applications Using Wireless Sensor Networks
by Kulathumani, Vinodkrishnan, Ph.D.  The Ohio State University. 2008: 226 pages; 10631197.
1 - 30 of 165 displayed.
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