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1.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
2.
Parallelization of Entity-Based Models in Computational Social Science: A Hardware Perspective
by Brearcliffe, Dale K., M.A.I.S.  George Mason University. 2017: 77 pages; 10684969.
3.
Algorithms and hardware designs for decimal multiplication
by Erle, Mark A., Ph.D.  Lehigh University. 2009: 229 pages; 3344791.
4.
Hardware acceleration of database applications
by Moussalli, Roger, Ph.D.  University of California, Riverside. 2013: 193 pages; 3559997.
5.
Hardware Transactional Memory: A Systems Perspective
by Rossbach, Christopher John, Ph.D.  The University of Texas at Austin. 2009: 204 pages; 3434949.
6.
Acceleration of Compute-Intensive Applications on Field Programmable Gate Arrays
by Rodríguez Borbón, Jose Milet , Ph.D.  University of California, Riverside. 2020: 161 pages; 27742586.
7.
Hardware Support for Productive Partitioned Global Address Space (PGAS) Programming
by Serres, Olivier, Ph.D.  The George Washington University. 2016: 122 pages; 3746724.
8.
Fast modular exponentiation using residue domain representation: A hardware implementation and analysis
by Nguyen, Christopher Dinh, M.S.  University of Maryland, Baltimore County. 2013: 129 pages; 1551346.
9.
Scheduling on Manycore and Heterogeneous Graphics Processors
by Tzeng, Stanley, Ph.D.  University of California, Davis. 2013: 119 pages; 3602240.
10.
Architectures for transactional memory
by McDonald, Austen, Ph.D.  Stanford University. 2009: 143 pages; 3364506.
11.
A Hardware-in-the-Loop Platform for DC Protection
by Vygoder, Mark, M.S.  The University of Wisconsin - Milwaukee. 2020: 109 pages; 27961677.
12.
Separating control from specification for parallel and distributed search algorithms
by See, Andrew G., Ph.D.  University of Connecticut. 2009: 173 pages; 3384551.
13.
Hardware Acceleration to Address the Costs of Data Movement
by Valavi, Hossein, Ph.D.  Princeton University. 2020: 254 pages; 27548046.
14.
Out-of-order Parallel Discrete Event Simulation for Electronic System-Level Design
by Chen, Weiwei, Ph.D.  University of California, Irvine. 2013: 194 pages; 3597427.
15.
Toward hardware-oriented defensive network infrastructure
by Chen, Hao, Ph.D.  State University of New York at Binghamton. 2015: 194 pages; 3713553.
16.
Tideflow: A dataflow-inspired execution model for high performance computing programs
by Orozco, Daniel A., Ph.D.  University of Delaware. 2012: 163 pages; 3527015.
17.
Parallel functional programming with mutable state
by Bergstrom, Lars, Ph.D.  The University of Chicago. 2013: 133 pages; 3568360.
18.
Real-time solid voxelization using multi-core pipelining
by Liao, Duoduo, Ph.D.  The George Washington University. 2009: 191 pages; 3344878.
19.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
20.
Enabling User Space Secure Hardware
by Coughlin, Aimee, Ph.D.  University of Colorado at Boulder. 2018: 137 pages; 10791863.
21.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
23.
Reverse converter design based on the New Chinese Remainder Theorem II using parallel prefix adders
by Sidda, Aditya, M.S.  California State University, Long Beach. 2016: 76 pages; 10182140.
24.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
25.
Effective scheduling techniques for high-level parallel programming languages
by Rainey, Michael Alan, Ph.D.  The University of Chicago. 2010: 143 pages; 3419774.
26.
Efficient primitives and algorithms for many-core architectures
by Sengupta, Shubhabrata, Ph.D.  University of California, Davis. 2010: 164 pages; 3444098.
27.
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler
by Lee, Yunsup, Ph.D.  University of California, Berkeley. 2016: 157 pages; 10151006.
28.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
29.
Fault tolerant parallel filters based on error correction codes
by Pulimi, Karthik, M.S.  California State University, Long Beach. 2017: 45 pages; 10262883.
30.
Invalidating Transactions: Optimizations, Theory, Guarantees, and Unification
by Gottschlich, Justin E., Ph.D.  University of Colorado at Boulder. 2011: 163 pages; 3453718.
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