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1.
Building Scalable Architectures Using Emerging Memory Technologies
by Korgaonkar, Kunal Kishore, Ph.D.  University of California, San Diego. 2019: 121 pages; 13882185.
2.
Novel Topologies for Highly-Scalable Non-volatile NEMS Relays
by Best, James T., Ph.D.  Carnegie Mellon University. 2019: 142 pages; 27671313.
3.
4.
Architecting emerging memory technologies for energy-efficient computing in modern processors
by Jianxing, Wang, Ph.D.  National University of Singapore (Singapore). 2015: 161 pages; 10006096.
5.
Comparative Analysis of Space-Grade Processors
by Lovelly, Tyler Michael, Ph.D.  University of Florida. 2017: 85 pages; 13847472.
6.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
7.
Scheduling on Manycore and Heterogeneous Graphics Processors
by Tzeng, Stanley, Ph.D.  University of California, Davis. 2013: 119 pages; 3602240.
8.
Simulation and characterization of inter-process interference on multithreaded and multicore architectures
by Kihm, Joshua Lee, Ph.D.  University of Colorado at Boulder. 2008: 309 pages; 3315818.
9.
Design for Competitive Automated Layout (DCAL) of Superscalar Processors
by Ku, Sungkwan, Ph.D.  North Carolina State University. 2017: 106 pages; 10970028.
10.
Verilog-A modeling of PMC memory cell
by Dimplu, Darshan Anandappa, M.S.  California State University, Long Beach. 2011: 60 pages; 1504425.
12.
Design Considerations for Nano-Electromechanical Relay Circuits
by Spencer, Matthew Edmund, Ph.D.  University of California, Berkeley. 2015: 102 pages; 3733438.
13.
Tideflow: A dataflow-inspired execution model for high performance computing programs
by Orozco, Daniel A., Ph.D.  University of Delaware. 2012: 163 pages; 3527015.
14.
An Automated System for Rapid and Secure Device Sanitization
by LaBarge, Ralph S., Ph.D.  The George Washington University. 2014: 113 pages; 3620600.
15.
The multiprocessor real -time scheduling of general task systems
by Fisher, Nathan Wayne, Ph.D.  The University of North Carolina at Chapel Hill. 2007: 254 pages; 3272810.
16.
Effective scheduling techniques for high-level parallel programming languages
by Rainey, Michael Alan, Ph.D.  The University of Chicago. 2010: 143 pages; 3419774.
17.
A parallel implementation of Gibbs sampling algorithm for 2PNO IRT models
by Rahimi, Mona, M.S.  Southern Illinois University at Carbondale. 2011: 72 pages; 1500979.
18.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
20.
Integrated hardware/software approaches to software security for embedded systems
by Gelbart, Olga, D.Sc.  The George Washington University. 2008: 137 pages; 3297440.
21.
Smart Writing of Programmable Metallization Cell
by Raval, Rizu, M.S.  California State University, Long Beach. 2018: 71 pages; 10786883.
22.
Building trust into utility cloud computing
by Krautheim, Frank John, Ph.D.  University of Maryland, Baltimore County. 2010: 144 pages; 3422891.
23.
A control framework for continuous time adaptation in modern day embedded systems
by Kallakuri, Sankalp, Ph.D.  State University of New York at Stony Brook. 2007: 147 pages; 3334943.
24.
Smart memories: A reconfigurable memory system architecture
by Firoozshahian, Amin, Ph.D.  Stanford University. 2009: 196 pages; 3343953.
25.
Reconfiguration of multiprocessor systems with spares using genetic algorithms
by Bollineni, Venugopal, M.S.  California State University, Long Beach. 2009: 50 pages; 1472282.
26.
A special unit to speed up a DSP processor
by Chenna Subbanagari, Uday Kumar Reddy, M.S.  California State University, Long Beach. 2016: 50 pages; 10108176.
27.
Topics in communication avoiding algorithms and stability analysis
by Lowery, Bradley R., Ph.D.  University of Colorado at Denver. 2014: 136 pages; 3621837.
28.
Extending Relativistic Programming to Multiple Writers
by Howard, Philip William, Ph.D.  Portland State University. 2012: 167 pages; 3502918.
29.
A Vector Parallel Branch and Bound Algorithm
by Guilbeau, Jared T., Ph.D.  University of Louisiana at Lafayette. 2016: 100 pages; 10242153.
30.
Parallel functional programming with mutable state
by Bergstrom, Lars, Ph.D.  The University of Chicago. 2013: 133 pages; 3568360.
1 - 30 of 2005 displayed.
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