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1.
Reduction of energy consumption on Network-On-Chip using a data encoding technique
by Gadde, Virinchi, M.S.  California State University, Long Beach. 2016: 43 pages; 10099873.
2.
Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs
by Reehal, Gursharan, Ph.D.  The Ohio State University. 2012: 190 pages; 10631229.
3.
Network-on-chip based h.264 video decoder on a field programmable gate array
by Barge, Ian J., M.S.  Marquette University. 2017: 78 pages; 10266086.
4.
Optimizing Network-on-Chip Designs for Heterogeneous Many-Core Architectures
by Le, Tung Thanh, Ph.D.  University of Louisiana at Lafayette. 2018: 97 pages; 10981900.
5.
Performance-Driven Communication Architecture Design in Irregular, Overlaid and Hybrid Mesh Wireless NoC
by Wu, Ruizhe, Ph.D.  University of Louisiana at Lafayette. 2014: 108 pages; 3622964.
6.
Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip
by Reza, Md Farhadur, Ph.D.  University of Louisiana at Lafayette. 2017: 154 pages; 10687409.
7.
Antikernel: A decentralized secure hardware-software operating system architecture
by Zonenberg, Andrew D., Ph.D.  Rensselaer Polytechnic Institute. 2015: 148 pages; 3705663.
8.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
9.
Performance-Driven Hierarchical Design and Management of Networks-on-Chip in Many-Core System
by Bai, Mingmin, Ph.D.  University of Louisiana at Lafayette. 2018: 81 pages; 13420526.
10.
Physical planning to embrace interconnect dominance in power and performance
by Wang, Renshen, Ph.D.  University of California, San Diego. 2010: 60 pages; 3404703.
11.
Contention Alleviation in Network-on-Chips
by Xiang, Xiyue, Ph.D.  University of Louisiana at Lafayette. 2017: 115 pages; 10272587.
12.
Parallelization of Entity-Based Models in Computational Social Science: A Hardware Perspective
by Brearcliffe, Dale K., M.A.I.S.  George Mason University. 2017: 77 pages; 10684969.
13.
14.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
15.
Performance enhancement of a multiprecision multiplier by a dynamic voltage scaling and multiprecision operands scheduling
by Bugata Venkata Phani Srirama, Kalyan Chakravarthy, M.S.  California State University, Long Beach. 2016: 38 pages; 10111181.
16.
A General Purpose Neural Processor
by Mountain, David Jerome, Ph.D.  University of Maryland, Baltimore County. 2017: 171 pages; 10268058.
17.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
18.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
19.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
20.
Design and Analysis of Large Scale Nanophotonic On-Chip Networks
by Nitta, Christopher, Ph.D.  University of California, Davis. 2011: 141 pages; 3499474.
21.
Characterizing Latencies of Edge Video Streaming
by Balhaj, Mohamed, M.S.  The University of North Carolina at Charlotte. 2017: 64 pages; 10280746.
22.
Robust Resource Allocation of Independent Tasks in Heterogeneous Computing Systems via Probabilistic Task Pruning
by Gentry, James A. S., M.S.  University of Louisiana at Lafayette. 2018: 88 pages; 10843501.
24.
Data Synchronizer Performance in the Presence of Parameter Variability
by Dunham, Samuel K., M.S.  Southern Illinois University at Edwardsville. 2014: 112 pages; 1566465.
25.
Software-Defined Architectures for Spectrally Efficient Cognitive Networking in Extreme Environments
by Sklivanitis, Georgios, Ph.D.  State University of New York at Buffalo. 2018: 182 pages; 10744705.
26.
Duty-Cycle Based Physical Unclonable Functions (PUFs) for Hardware Security Applications
by Azhar, Mahmood Javed, Ph.D.  University of South Florida. 2018: 100 pages; 10980455.
27.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
28.
A control framework for continuous time adaptation in modern day embedded systems
by Kallakuri, Sankalp, Ph.D.  State University of New York at Stony Brook. 2007: 147 pages; 3334943.
29.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
30.
Enhancing silicon debug techniques via DFD hardware insertion
by Yang, Joon Sung, Ph.D.  The University of Texas at Austin. 2009: 118 pages; 3372679.
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