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1.
Enabling dynamic voltage and frequency scaling in multicore architectures
by Prasad, Amithash, M.S.  University of Colorado at Boulder. 2009: 74 pages; 1473683.
2.
Comparative Analysis of Space-Grade Processors
by Lovelly, Tyler Michael, Ph.D.  University of Florida. 2017: 85 pages; 13847472.
3.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
4.
A study of a data parallel algorithm for XML DOM parsing
by Shah, Bhavik Bharatkumar, M.S.  University of Missouri - Kansas City. 2009: 50 pages; 1478718.
5.
A control-theoretic design and analysis framework for resilient hard real-time systems
by Hettiarachchi, Pradeep M., Ph.D.  Wayne State University. 2015: 167 pages; 3723517.
6.
Real-time solid voxelization using multi-core pipelining
by Liao, Duoduo, Ph.D.  The George Washington University. 2009: 191 pages; 3344878.
7.
Tideflow: A dataflow-inspired execution model for high performance computing programs
by Orozco, Daniel A., Ph.D.  University of Delaware. 2012: 163 pages; 3527015.
8.
Simulation and characterization of inter-process interference on multithreaded and multicore architectures
by Kihm, Joshua Lee, Ph.D.  University of Colorado at Boulder. 2008: 309 pages; 3315818.
9.
High performance methods for frequent pattern mining
by Vu, Lan, Ph.D.  University of Colorado at Denver. 2014: 190 pages; 3667246.
10.
Performance comparison of multiprocessor programming libraries for multicore environments
by Pien, Hu Yun, M.S.  California State University, Long Beach. 2012: 68 pages; 1520921.
11.
Leveraging Model-Based Techniques for Component Level Architecture Analysis in Product-Based Systems
by McKean, David Keith, Ph.D.  The George Washington University. 2019: 209 pages; 13812870.
12.
Programmable and Scalable Software-Defined Networking Controllers
by Voellmy, Andreas Richard, Ph.D.  Yale University. 2014: 219 pages; 3580888.
13.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
14.
Spatial Division Multiplexed Transmission and Sensing in Few-Mode Fibers
by Weng, Yi, Ph.D.  University of Louisiana at Lafayette. 2017: 136 pages; 10261316.
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16.
Smart memories: A reconfigurable memory system architecture
by Firoozshahian, Amin, Ph.D.  Stanford University. 2009: 196 pages; 3343953.
18.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
19.
Symbiotic virtualization
by Lange, John Russell, Ph.D.  Northwestern University. 2010: 224 pages; 3426601.
20.
Automatically tuning collective communication for one-sided programming models
by Nishtala, Rajesh, Ph.D.  University of California, Berkeley. 2009: 176 pages; 3402682.
21.
Developing physics simulations with OpenCL on a graphics processing unit
by Perelygin, Kyrylo, M.S.  California State University, Long Beach. 2012: 74 pages; 1522252.
22.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
23.
Effective Checkpointing for Networked Multicore Systems and Cloud Computing
by Jangjaimon, Itthichok, Ph.D.  University of Louisiana at Lafayette. 2013: 114 pages; 3615289.
24.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
25.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
26.
Towards a systematic study of big data performance and benchmarking
by Ekanayake, Saliya, Ph.D.  Indiana University. 2016: 120 pages; 10195564.
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28.
Contention Alleviation in Network-on-Chips
by Xiang, Xiyue, Ph.D.  University of Louisiana at Lafayette. 2017: 115 pages; 10272587.
30.
Efficient ray tracing architectures
by Spjut, Josef Bo, Ph.D.  The University of Utah. 2015: 129 pages; 3727095.
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