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1.
Design for Competitive Automated Layout (DCAL) of Superscalar Processors
by Ku, Sungkwan, Ph.D.  North Carolina State University. 2017: 106 pages; 10970028.
2.
Enhanced Secondary Bus Microarchitecture
by O'Farrell, John William, Ph.D.  Auburn University. 2011: 96 pages; 3480707.
3.
Contention Alleviation in Network-on-Chips
by Xiang, Xiyue, Ph.D.  University of Louisiana at Lafayette. 2017: 115 pages; 10272587.
4.
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler
by Lee, Yunsup, Ph.D.  University of California, Berkeley. 2016: 157 pages; 10151006.
5.
Performance-Driven Hierarchical Design and Management of Networks-on-Chip in Many-Core System
by Bai, Mingmin, Ph.D.  University of Louisiana at Lafayette. 2018: 81 pages; 13420526.
6.
Leveraging Model-Based Techniques for Component Level Architecture Analysis in Product-Based Systems
by McKean, David Keith, Ph.D.  The George Washington University. 2019: 209 pages; 13812870.
7.
Toward a software pipelining framework for many-core chips
by Ributzka, Juergen, M.S.  University of Delaware. 2009: 97 pages; 1469538.
10.
The effects of sex steroids and reactive oxygen species on the maintenance of the skeleton
by Ucer, Semahat Serra, Ph.D.  University of Arkansas for Medical Sciences. 2016: 136 pages; 10146404.
11.
Analysis of Principal Structural Orientation of Trabecular Bone Using Quantitative Ultrasound
by Lin, Liangjun, Ph.D.  State University of New York at Stony Brook. 2014: 129 pages; 3642410.
12.
Gray Matter Surface-Based Spatial Statistics in Neuroimaging Studies
by Parvathaneni, Prasanna, Ph.D.  Vanderbilt University. 2019: 171 pages; 13810802.
13.
Building Scalable Architectures Using Emerging Memory Technologies
by Korgaonkar, Kunal Kishore, Ph.D.  University of California, San Diego. 2019: 121 pages; 13882185.
14.
Dynamic Trace Analysis with Zero-Suppressed BDDs
by Price, Graham David, Ph.D.  University of Colorado at Boulder. 2011: 224 pages; 3468482.
15.
17.
Heterogeneity and Density Aware Design of Computing Systems
by Arora, Manish, Ph.D.  University of California, San Diego. 2018: 137 pages; 10788835.
18.
Using locality and interleaving information to improve shared cache performance
by Liu, Wanli, Ph.D.  University of Maryland, College Park. 2009: 140 pages; 3359458.
19.
Architecting emerging memory technologies for energy-efficient computing in modern processors
by Jianxing, Wang, Ph.D.  National University of Singapore (Singapore). 2015: 161 pages; 10006096.
20.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
21.
Simulation and characterization of inter-process interference on multithreaded and multicore architectures
by Kihm, Joshua Lee, Ph.D.  University of Colorado at Boulder. 2008: 309 pages; 3315818.
22.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
23.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
24.
Intelligent cache management techniques for reducing memory systemwaste
by Khan, Samira M., Ph.D.  The University of Texas at San Antonio. 2012: 109 pages; 3527415.
25.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
26.
SRAM reliability improvement using ECC and circuit techniques
by McCartney, Mark P., Ph.D.  Carnegie Mellon University. 2014: 131 pages; 3733956.
27.
Approximating application performances in cloud data centers and simulated machines
by Islam, Mohammad Shahedul, Ph.D.  The University of Texas at San Antonio. 2016: 113 pages; 10249769.
28.
Enabling dynamic voltage and frequency scaling in multicore architectures
by Prasad, Amithash, M.S.  University of Colorado at Boulder. 2009: 74 pages; 1473683.
29.
Reconfigurable computing: Power consumption optimization in embedded systems
by Varadarajan, Srihari, M.S.  California State University, Long Beach. 2014: 78 pages; 1569997.
30.
Hardware Transactional Memory: A Systems Perspective
by Rossbach, Christopher John, Ph.D.  The University of Texas at Austin. 2009: 204 pages; 3434949.
1 - 30 of 166 displayed.
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