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1.
On-chip demonstration of carbon nanotube interconnects
by Close, Gael F., Ph.D.  Stanford University. 2008: 134 pages; 3313812.
2.
A gigabit multi-drop interconnect with impedance matching network
by Ye, Zhijing, M.S.  Southern Methodist University. 2016: 47 pages; 10109007.
3.
Silicon Micro-ring Resonator Device Design for Optical Interconnect Systems
by Li, Yunchu, Ph.D.  University of Southern California. 2013: 110 pages; 3563933.
4.
Physical planning to embrace interconnect dominance in power and performance
by Wang, Renshen, Ph.D.  University of California, San Diego. 2010: 60 pages; 3404703.
5.
Integration of atomic layer deposition-grown copper for advanced interconnect applications
by Wu, Liqi, Ph.D.  State University of New York at Albany. 2008: 167 pages; 3327486.
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Design Automation for Carbon Nanotube Circuits Considering Performance and Security Optimization
by Liu, Lin, Ph.D.  Michigan Technological University. 2017: 169 pages; 10267186.
11.
Electron Scattering at Surfaces and Interfaces of Transition Metals
by Zheng, Pengyuan, Ph.D.  Rensselaer Polytechnic Institute. 2015: 113 pages; 10010793.
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13.
Direct write fabrication of waveguides and interconnects for optical printed wiring boards
by Dingeldein, Joseph C., Ph.D.  Michigan Technological University. 2012: 107 pages; 3542522.
14.
Microgripper force feedback integration using piezoresistive cantilever structure
by Simon, Todd R., M.S.  Rochester Institute of Technology. 2008: 86 pages; 1460282.
15.
Energy Efficient Oxide Confined VCSELs for Optical Interconnects in Data Centers and Supercomputers
by Moser, Philip, Dr.Nat.  Technische Universitaet Berlin (Germany). 2015: 202 pages; 10697855.
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Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip
by Reza, Md Farhadur, Ph.D.  University of Louisiana at Lafayette. 2017: 154 pages; 10687409.
18.
Improvement of a propagation delay model for CMOS digital logic circuits
by Stamness, Rodger Lawrence, M.S.  San Jose State University. 2010: 100 pages; 1477363.
19.
The neural dogma
by Merrill, Bradford Chester, M.A.  University of Nevada, Reno. 2008: 128 pages; 1460809.
21.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
22.
Effect of joule heating on the reliability of stamped metal land grid array sockets
by Challa, Vidyullatha, Ph.D.  University of Maryland, College Park. 2010: 109 pages; 3443431.
23.
Rapid laser crystallization of semiconductors for three-dimensional integration
by Witte, Daniel Jonathan, Ph.D.  Stanford University. 2009: 177 pages; 3364516.
24.
Experiments on an Automotive Electronic Control Unit Using a Controller Area Network Bus
by Tou, Johnny, M.S.  California State University, Long Beach. 2018: 70 pages; 10751912.
25.
Three-Dimensional Inkjet-Printed Metal Nanoparticles: Ink and Application Development
by Sadie, Jacob Alexander, Ph.D.  University of California, Berkeley. 2015: 158 pages; 10187734.
27.
Incorporating the effect of delay variability in path based delay testing
by Tayade, Rajeshwary G., Ph.D.  The University of Texas at Austin. 2009: 180 pages; 3371817.
28.
Modeling and design of high-performance and power-efficient 3D dram architectures
by Chen, Ke, Ph.D.  University of Notre Dame. 2013: 151 pages; 3732210.
29.
Assessment of Properties of Transient Liquid Phase Sintered (TLPS) Interconnects by Simulation and Experiments
by Greve, Hannes Martin Hinrich, Ph.D.  University of Maryland, College Park. 2017: 320 pages; 10270347.
30.
Architectures for transactional memory
by McDonald, Austen, Ph.D.  Stanford University. 2009: 143 pages; 3364506.
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