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1.
Real time target allocation in cooperative unmanned aerial vehicles
by Kudleppanavar, Ganesh, M.S.  California State University, Long Beach. 2015: 41 pages; 1603968.
2.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
3.
Hardware/Software Co-Design via Specification Refinement
by Peck, Wesley G., Ph.D.  University of Kansas. 2011: 183 pages; 3489442.
4.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
5.
Putnam County's Credit Recovery Program: A Review of Implementation of Compass Learning
by Siciensky, Emily||||||Green, Toriano||||||Agee, Seth, Ed.D.  Lipscomb University. 2014: 209 pages; 3646801.
6.
Application hardware-software co-design for reconfigurable computing systems
by Saha, Proshanta, Ph.D.  The George Washington University. 2008: 151 pages; 3297468.
8.
Fast modular exponentiation using residue domain representation: A hardware implementation and analysis
by Nguyen, Christopher Dinh, M.S.  University of Maryland, Baltimore County. 2013: 129 pages; 1551346.
9.
The effect of part-task and whole-task training on air traffic controller communication complexity
by Arnsdorff, G. Blake, M.S.  California State University, Long Beach. 2016: 76 pages; 10096076.
10.
The Hybrid Task Graph Scheduler
by Blattner, Timothy, Ph.D.  University of Maryland, Baltimore County. 2016: 152 pages; 10245475.
11.
Acceleration of Compute-Intensive Applications on Field Programmable Gate Arrays
by Rodríguez Borbón, Jose Milet , Ph.D.  University of California, Riverside. 2020: 161 pages; 27742586.
12.
Enabling User Space Secure Hardware
by Coughlin, Aimee, Ph.D.  University of Colorado at Boulder. 2018: 137 pages; 10791863.
13.
Queue Streaming Model: Theory, Algorithms, and Implementation
by Zope, Anup D., Ph.D.  Mississippi State University. 2019: 215 pages; 13860290.
15.
Hardware acceleration of database applications
by Moussalli, Roger, Ph.D.  University of California, Riverside. 2013: 193 pages; 3559997.
18.
Accuracy evaluation of power hardware-in-the-loop (PHIL) simulation
by Ren, Wei, Ph.D.  The Florida State University. 2007: 77 pages; 3301588.
19.
Control Design and Implementation of an Active Transtibial Prosthesis
by Klein, Joseph G., M.S.  Marquette University. 2018: 132 pages; 10839035.
20.
Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D.  University of California, Berkeley. 2016: 153 pages; 10150942.
23.
Design and implementation of biomesensi software platform
by Parameshwaran, Keerthi, M.S.  California State University, Long Beach. 2015: 94 pages; 1596989.
24.
Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S.  California State University, Long Beach. 2016: 80 pages; 10196051.
25.
Toward hardware-oriented defensive network infrastructure
by Chen, Hao, Ph.D.  State University of New York at Binghamton. 2015: 194 pages; 3713553.
26.
The Impact of Professional Development on Early Implementation of a 1:1 Laptop Initiative
by Hanson, Bradley A., Ed.D.  Lindenwood University. 2015: 195 pages; 3728020.
27.
Transformation of governmental organizations: The case of the California Integrated Waste Management Board
by Eowan, George T., Ph.D.  University of Southern California. 2009: 224 pages; 3355412.
28.
Hardware Acceleration to Address the Costs of Data Movement
by Valavi, Hossein, Ph.D.  Princeton University. 2020: 254 pages; 27548046.
29.
Detection of Boundary Layer Separation and Implementation of Autonomous Vortex Generators
by Morice, Samuel Davis, M.S.  University of California, Davis. 2019: 79 pages; 27539485.
30.
The Impact of Task Load on Neural Entrainment to Attended Speech: a Dual-Task Magnetoencephalography (MEG) Paradigm
by Kassel, Michelle T., Ph.D.  The University of Wisconsin - Milwaukee. 2020: 97 pages; 28091271.
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