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1.
Real time target allocation in cooperative unmanned aerial vehicles
by Kudleppanavar, Ganesh, M.S.  California State University, Long Beach. 2015: 41 pages; 1603968.
2.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
3.
Application hardware-software co-design for reconfigurable computing systems
by Saha, Proshanta, Ph.D.  The George Washington University. 2008: 151 pages; 3297468.
4.
Enabling User Space Secure Hardware
by Coughlin, Aimee, Ph.D.  University of Colorado at Boulder. 2018: 137 pages; 10791863.
5.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
6.
The Hybrid Task Graph Scheduler
by Blattner, Timothy, Ph.D.  University of Maryland, Baltimore County. 2016: 152 pages; 10245475.
7.
Putnam County's Credit Recovery Program: A Review of Implementation of Compass Learning
by Siciensky, Emily||||||Green, Toriano||||||Agee, Seth, Ed.D.  Lipscomb University. 2014: 209 pages; 3646801.
8.
Scheduling on Manycore and Heterogeneous Graphics Processors
by Tzeng, Stanley, Ph.D.  University of California, Davis. 2013: 119 pages; 3602240.
9.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
10.
Parallelization of lane detection algorithm using OpenCL
by Kalay, Harshal A., M.S.  California State University, Long Beach. 2015: 106 pages; 1603755.
11.
Effective scheduling techniques for high-level parallel programming languages
by Rainey, Michael Alan, Ph.D.  The University of Chicago. 2010: 143 pages; 3419774.
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Hardware/Software Co-Design via Specification Refinement
by Peck, Wesley G., Ph.D.  University of Kansas. 2011: 183 pages; 3489442.
15.
Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D.  University of California, Berkeley. 2016: 153 pages; 10150942.
16.
Performance comparison of multiprocessor programming libraries for multicore environments
by Pien, Hu Yun, M.S.  California State University, Long Beach. 2012: 68 pages; 1520921.
17.
Mitigating Privilege Escalation
by Brookes, Scott, Ph.D.  Dartmouth College. 2018: 215 pages; 10822683.
18.
Opportunities for near data computing in MapReduce workloads
by Pugsley, Seth Hintze, Ph.D.  The University of Utah. 2015: 98 pages; 3704952.
19.
Symbiotic virtualization
by Lange, John Russell, Ph.D.  Northwestern University. 2010: 224 pages; 3426601.
20.
Tideflow: A dataflow-inspired execution model for high performance computing programs
by Orozco, Daniel A., Ph.D.  University of Delaware. 2012: 163 pages; 3527015.
21.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
23.
Hardware Support for Productive Partitioned Global Address Space (PGAS) Programming
by Serres, Olivier, Ph.D.  The George Washington University. 2016: 122 pages; 3746724.
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Scheduling and locking in multiprocessor real-time operating systems
by Brandenburg, Bjorn B., Ph.D.  The University of North Carolina at Chapel Hill. 2011: 614 pages; 3502550.
27.
Scalable virtual machine multiplexing
by Gupta, Diwaker, Ph.D.  University of California, San Diego. 2009: 183 pages; 3338860.
28.
Benchhub: Store Database Benchmark Result in Database
by Guo, Pinglei, M.S.  University of California, Santa Cruz. 2018: 58 pages; 10749082.
29.
Robotic control: Real-time architectures and multi-flock flocking
by McKenzie, Andrew W., Ph.D.  The University of Alabama. 2012: 92 pages; 3511053.
30.
A control-theoretic design and analysis framework for resilient hard real-time systems
by Hettiarachchi, Pradeep M., Ph.D.  Wayne State University. 2015: 167 pages; 3723517.
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