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1.
FinFET memory cell improvements for higher immunity against single event upsets
by Sajit, Ahmed Sattar, M.S.  California State University, Fullerton. 2016: 63 pages; 10244875.
2.
Substrate Heating During Channel Formation in Nano Scale MOSFET
by Athmakur, Abhiram Goud, M.S.  University of Louisiana at Lafayette. 2013: 66 pages; 1553872.
3.
III-V and 2D Devices: From MOSFETs to Steep-Slope Transistors
by Si, Mengwei, Ph.D.  Purdue University. 2018: 148 pages; 10838712.
4.
An Assessment of Critical Dimension Small Angle X-ray Scattering Metrology for Advanced Semiconductor Manufacturing
by Settens, Charles M., Ph.D.  State University of New York at Albany. 2015: 239 pages; 3701713.
5.
The Nanoscale Optical Properties of Complex Nanostructures
by Hachtel, Jordan Adam, Ph.D.  Vanderbilt University. 2016: 179 pages; 13834896.
6.
Energy of Formation of Step Junctions at Nano Dimensions
by Kawatkar, Prasanna Ulhas, M.S.  University of Louisiana at Lafayette. 2013: 70 pages; 1553878.
7.
Novel III-V device architectures for application in advance CMOS logic and beyond
by Hui, Goh Kian, Ph.D.  National University of Singapore (Singapore). 2015: 185 pages; 10006003.
9.
Probe immobilization strategies and device optimization for novel transistor-based DNA sensors
by Fahrenkopf, Nicholas M., Ph.D.  State University of New York at Albany. 2013: 157 pages; 3558154.
10.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
11.
Design Considerations for Nano-Electromechanical Relay Circuits
by Spencer, Matthew Edmund, Ph.D.  University of California, Berkeley. 2015: 102 pages; 3733438.
12.
Experimental Investigations of Thermal Transport in Carbon Nanotubes, Graphene and Nanoscale Point Contacts
by Pettes, Michael Thompson, Ph.D.  The University of Texas at Austin. 2011: 163 pages; 3484428.
13.
Heterogeneity and Density Aware Design of Computing Systems
by Arora, Manish, Ph.D.  University of California, San Diego. 2018: 137 pages; 10788835.
14.
Theoretical analysis of prospective nanoelectronic devices
by Walls, Thomas John, Ph.D.  State University of New York at Stony Brook. 2008: 230 pages; 3406710.
15.
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler
by Lee, Yunsup, Ph.D.  University of California, Berkeley. 2016: 157 pages; 10151006.
1 - 15 of 15 displayed.
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