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1.
Reliability-Aware Placement and Routing for FPGAs
by Abdul-Aziz, Mohammed A., M.S.  Northeastern University. 2010: 94 pages; 1489294.
2.
Reliability-Aware CAD Tools for SRAM-Based FPGAs
by Golshan, Shahin, Ph.D.  University of California, Irvine. 2011: 148 pages; 3481525.
3.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
4.
Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA's
by Pathanjali, Nandini, M.S.  University of Cincinnati. 2002: 110 pages; 10857176.
5.
Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
6.
Reconfigurable computing: Power consumption optimization in embedded systems
by Varadarajan, Srihari, M.S.  California State University, Long Beach. 2014: 78 pages; 1569997.
7.
Comparative Analysis of Space-Grade Processors
by Lovelly, Tyler Michael, Ph.D.  University of Florida. 2017: 85 pages; 13847472.
8.
Application hardware-software co-design for reconfigurable computing systems
by Saha, Proshanta, Ph.D.  The George Washington University. 2008: 151 pages; 3297468.
9.
Development, Optimization, and Integration of Inline Phase-Change Switches for Reconfigurable RF Systems
by El-Hinnawy, Nabil A., Ph.D.  Carnegie Mellon University. 2018: 119 pages; 10817464.
10.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
11.
Enabling User Space Secure Hardware
by Coughlin, Aimee, Ph.D.  University of Colorado at Boulder. 2018: 137 pages; 10791863.
12.
Hardware acceleration of database applications
by Moussalli, Roger, Ph.D.  University of California, Riverside. 2013: 193 pages; 3559997.
15.
Fast modular exponentiation using residue domain representation: A hardware implementation and analysis
by Nguyen, Christopher Dinh, M.S.  University of Maryland, Baltimore County. 2013: 129 pages; 1551346.
16.
Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S.  California State University, Long Beach. 2016: 80 pages; 10196051.
17.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
18.
Toward a Hardware Accelerated Future
by Lyons, Michael John, Ph.D.  Harvard University. 2013: 162 pages; 3600206.
19.
NodeBlaze: Using reprogrammable logic to advance sensor networking technology
by Gruenwald, Charles, M.S.  University of Colorado at Boulder. 2007: 57 pages; 1447677.
20.
Integrated hardware/software approaches to software security for embedded systems
by Gelbart, Olga, D.Sc.  The George Washington University. 2008: 137 pages; 3297440.
21.
An Investigation of an Open-IP Linux Architecture
by Edmiston, Christopher C., M.S.  Southern Illinois University at Edwardsville. 2014: 68 pages; 1568355.
22.
Toward hardware-oriented defensive network infrastructure
by Chen, Hao, Ph.D.  State University of New York at Binghamton. 2015: 194 pages; 3713553.
23.
Network-on-chip based h.264 video decoder on a field programmable gate array
by Barge, Ian J., M.S.  Marquette University. 2017: 78 pages; 10266086.
24.
An optimized modified booth recoder for efficient design of the add-multiply operator
by Mehta, Kunal, M.S.  California State University, Long Beach. 2015: 35 pages; 1603343.
25.
Antikernel: A decentralized secure hardware-software operating system architecture
by Zonenberg, Andrew D., Ph.D.  Rensselaer Polytechnic Institute. 2015: 148 pages; 3705663.
26.
28.
Database Streaming Compression on Memory-Limited Machines
by Bruccoleri, Damon, Ph.D.  Nova Southeastern University. 2018: 208 pages; 10751913.
29.
Hardware Support for Productive Partitioned Global Address Space (PGAS) Programming
by Serres, Olivier, Ph.D.  The George Washington University. 2016: 122 pages; 3746724.
30.
An efficient architecture for adaptive finite impulse response filters on field programmable gate arrays
by Nallani Chakravartula, Krishna Chaitanya, M.S.  California State University, Long Beach. 2016: 56 pages; 10137445.
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