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1.
Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip
by Reza, Md Farhadur, Ph.D.  University of Louisiana at Lafayette. 2017: 154 pages; 10687409.
2.
Antikernel: A decentralized secure hardware-software operating system architecture
by Zonenberg, Andrew D., Ph.D.  Rensselaer Polytechnic Institute. 2015: 148 pages; 3705663.
3.
Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D.  University of California, Berkeley. 2016: 153 pages; 10150942.
4.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
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6.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
7.
Low Power Techniques for Video Codec Motion Compensation
by Badran-Louca, Serena, Ph.D.  North Carolina State University. 2015: 74 pages; 3710728.
8.
Optimizing Network-on-Chip Designs for Heterogeneous Many-Core Architectures
by Le, Tung Thanh, Ph.D.  University of Louisiana at Lafayette. 2018: 97 pages; 10981900.
9.
Early Prediction of Epilepsy Seizure via VLSI BCI Based System
by ElSayed, Zaghloul, Ph.D.  University of Louisiana at Lafayette. 2016: 174 pages; 10163299.
10.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
11.
System on chip: Two design paths explained
by Tamayo, Jose, M.S.  California State University, Long Beach. 2012: 99 pages; 1520930.
12.
On-Chip Diagnosis of Generalized Delay Failures using Compact Fault Dictionaries
by Beckler, Matthew Layne, Ph.D.  Carnegie Mellon University. 2017: 132 pages; 10283822.
13.
Design and Analysis of Large Scale Nanophotonic On-Chip Networks
by Nitta, Christopher, Ph.D.  University of California, Davis. 2011: 141 pages; 3499474.
14.
Performance-Driven Hierarchical Design and Management of Networks-on-Chip in Many-Core System
by Bai, Mingmin, Ph.D.  University of Louisiana at Lafayette. 2018: 81 pages; 13420526.
15.
Network-on-chip based h.264 video decoder on a field programmable gate array
by Barge, Ian J., M.S.  Marquette University. 2017: 78 pages; 10266086.
16.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
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18.
Efficient ray tracing architectures
by Spjut, Josef Bo, Ph.D.  The University of Utah. 2015: 129 pages; 3727095.
19.
Contention Alleviation in Network-on-Chips
by Xiang, Xiyue, Ph.D.  University of Louisiana at Lafayette. 2017: 115 pages; 10272587.
20.
Opportunities for near data computing in MapReduce workloads
by Pugsley, Seth Hintze, Ph.D.  The University of Utah. 2015: 98 pages; 3704952.
21.
The mechanisms responsible for the genomic recruitment of E2F1
by Cao, Alina Rabinovich, Ph.D.  University of California, Davis. 2010: 215 pages; 3427480.
22.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
23.
Heterogeneity and Density Aware Design of Computing Systems
by Arora, Manish, Ph.D.  University of California, San Diego. 2018: 137 pages; 10788835.
24.
Hardware Acceleration to Address the Costs of Data Movement
by Valavi, Hossein, Ph.D.  Princeton University. 2020: 254 pages; 27548046.
25.
Ultra-Low Power RFIC for Space/Medical/Mobile Applications
by Yasami, Saeid, Ph.D.  University of Louisiana at Lafayette. 2015: 114 pages; 10003754.
26.
Reliability-Aware CAD Tools for SRAM-Based FPGAs
by Golshan, Shahin, Ph.D.  University of California, Irvine. 2011: 148 pages; 3481525.
27.
Design For Test for OSU Standard Cell Library Used at GWU
by Gibb, William, M.S.  The George Washington University. 2014: 74 pages; 1560525.
29.
A study on the feasibility of universal chip control in machining
by Kumbera Ganapathi, Thimmaiah, Ph.D.  Michigan Technological University. 2011: 241 pages; 3454088.
30.
Unlocking Design Reuse with Hardware Compiler Frameworks
by Izraelevitz, Adam, Ph.D.  University of California, Berkeley. 2019: 150 pages; 27663969.
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