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1.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
2.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
3.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
4.
Using locality and interleaving information to improve shared cache performance
by Liu, Wanli, Ph.D.  University of Maryland, College Park. 2009: 140 pages; 3359458.
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Enabling dynamic voltage and frequency scaling in multicore architectures
by Prasad, Amithash, M.S.  University of Colorado at Boulder. 2009: 74 pages; 1473683.
8.
Design and architecture of automatically-generated energy-reducing coprocessors
by Sampson, John Morgan, Ph.D.  University of California, San Diego. 2010: 119 pages; 3422889.
9.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
10.
Smart memories: A reconfigurable memory system architecture
by Firoozshahian, Amin, Ph.D.  Stanford University. 2009: 196 pages; 3343953.
11.
Intelligent cache management techniques for reducing memory systemwaste
by Khan, Samira M., Ph.D.  The University of Texas at San Antonio. 2012: 109 pages; 3527415.
12.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
13.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
15.
Heterogeneity and Density Aware Design of Computing Systems
by Arora, Manish, Ph.D.  University of California, San Diego. 2018: 137 pages; 10788835.
18.
Joint Reliability and Energy Management for Real-Time Embedded Systems
by Zhao, Baoxian, Ph.D.  George Mason University. 2012: 170 pages; 3522025.
19.
Performance-Driven Communication Architecture Design in Irregular, Overlaid and Hybrid Mesh Wireless NoC
by Wu, Ruizhe, Ph.D.  University of Louisiana at Lafayette. 2014: 108 pages; 3622964.
20.
Optimizing Network-on-Chip Designs for Heterogeneous Many-Core Architectures
by Le, Tung Thanh, Ph.D.  University of Louisiana at Lafayette. 2018: 97 pages; 10981900.
21.
Simulation and characterization of inter-process interference on multithreaded and multicore architectures
by Kihm, Joshua Lee, Ph.D.  University of Colorado at Boulder. 2008: 309 pages; 3315818.
22.
Software modulated fault tolerance
by Reis, George A., III, Ph.D.  Princeton University. 2008: 104 pages; 3308327.
23.
Contention Alleviation in Network-on-Chips
by Xiang, Xiyue, Ph.D.  University of Louisiana at Lafayette. 2017: 115 pages; 10272587.
24.
Criticality Assessments for Improving Algorithmic Robustness
by Jones, Thomas Berry, Ph.D.  The University of New Mexico. 2018: 190 pages; 10980232.
25.
Silicon Micro-ring Resonator Device Design for Optical Interconnect Systems
by Li, Yunchu, Ph.D.  University of Southern California. 2013: 110 pages; 3563933.
26.
Queue Streaming Model: Theory, Algorithms, and Implementation
by Zope, Anup D., Ph.D.  Mississippi State University. 2019: 215 pages; 13860290.
27.
A control-theoretic design and analysis framework for resilient hard real-time systems
by Hettiarachchi, Pradeep M., Ph.D.  Wayne State University. 2015: 167 pages; 3723517.
28.
Modeling and design of high-performance and power-efficient 3D dram architectures
by Chen, Ke, Ph.D.  University of Notre Dame. 2013: 151 pages; 3732210.
29.
Enabling increased complexity for realistic image synthesis
by Budge, Brian Christopher, Ph.D.  University of California, Davis. 2009: 136 pages; 3396900.
30.
An Approach for Designing Secure and High Performance Cloud Systems
by Gai, Keke, Ph.D.  Pace University. 2017: 221 pages; 10635446.
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