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1.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
2.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
3.
The multiprocessor real -time scheduling of general task systems
by Fisher, Nathan Wayne, Ph.D.  The University of North Carolina at Chapel Hill. 2007: 254 pages; 3272810.
4.
Scheduling and locking in multiprocessor real-time operating systems
by Brandenburg, Bjorn B., Ph.D.  The University of North Carolina at Chapel Hill. 2011: 614 pages; 3502550.
5.
Toward a software pipelining framework for many-core chips
by Ributzka, Juergen, M.S.  University of Delaware. 2009: 97 pages; 1469538.
6.
A Smart Design Framework for a Novel Reconfigurable Multi-Processor Systems-on-Chip (ASREM) Architecture
by Dutta, Anandi, Ph.D.  University of Louisiana at Lafayette. 2016: 127 pages; 10163349.
8.
Flexible Architectures for Enhanced Security
by Chang, Jed Kao-Tung, Ph.D.  University of California, Irvine. 2012: 149 pages; 3518799.
9.
Efficient ray tracing architectures
by Spjut, Josef Bo, Ph.D.  The University of Utah. 2015: 129 pages; 3727095.
10.
A study on the feasibility of universal chip control in machining
by Kumbera Ganapathi, Thimmaiah, Ph.D.  Michigan Technological University. 2011: 241 pages; 3454088.
11.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
12.
Performance-Driven Hierarchical Design and Management of Networks-on-Chip in Many-Core System
by Bai, Mingmin, Ph.D.  University of Louisiana at Lafayette. 2018: 81 pages; 13420526.
13.
Real-time solid voxelization using multi-core pipelining
by Liao, Duoduo, Ph.D.  The George Washington University. 2009: 191 pages; 3344878.
14.
Computation and Communication Optimization in Many-Core Heterogeneous Server-on-Chip
by Reza, Md Farhadur, Ph.D.  University of Louisiana at Lafayette. 2017: 154 pages; 10687409.
15.
Smart memories: A reconfigurable memory system architecture
by Firoozshahian, Amin, Ph.D.  Stanford University. 2009: 196 pages; 3343953.
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Fault-tolerant FPGA-based multi-processor systems for nano-satellites
by Venkataraman, Shyamsunda, M.Eng.  National University of Singapore (Singapore). 2015: 94 pages; 10006079.
18.
Design and Analysis of Large Scale Nanophotonic On-Chip Networks
by Nitta, Christopher, Ph.D.  University of California, Davis. 2011: 141 pages; 3499474.
19.
Performance comparison of multiprocessor programming libraries for multicore environments
by Pien, Hu Yun, M.S.  California State University, Long Beach. 2012: 68 pages; 1520921.
20.
Parallelizing a data intensive Lagrangian stochastic particle model using graphics processing units
by Hurst, Jonathan George, M.S.  University of Colorado at Boulder. 2010: 101 pages; 1481219.
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22.
Thermal analysis for nanometer-scale integrated circuits
by Hassan, Zyad, M.S.  University of Colorado at Boulder. 2009: 98 pages; 1473684.
23.
Performance-Driven Communication Architecture Design in Irregular, Overlaid and Hybrid Mesh Wireless NoC
by Wu, Ruizhe, Ph.D.  University of Louisiana at Lafayette. 2014: 108 pages; 3622964.
24.
Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips
by Shamshiri, Saeed, Ph.D.  University of California, Santa Barbara. 2011: 178 pages; 3473795.
25.
Heterogeneity and Density Aware Design of Computing Systems
by Arora, Manish, Ph.D.  University of California, San Diego. 2018: 137 pages; 10788835.
26.
Thermal management and electromechanical noise suppression in a portable josephson junction voltage standard
by Singh, Namit, Ph.D.  The University of North Carolina at Charlotte. 2012: 131 pages; 3551945.
27.
Hardware Transactional Memory: A Systems Perspective
by Rossbach, Christopher John, Ph.D.  The University of Texas at Austin. 2009: 204 pages; 3434949.
29.
Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D.  University of California, Berkeley. 2016: 153 pages; 10150942.
30.
Acceleration of streaming applications on FPGAs from high level constructs
by Mitra, Abhishek, Ph.D.  University of California, Riverside. 2008: 192 pages; 3341851.
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