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2.
Using locality and interleaving information to improve shared cache performance
by Liu, Wanli, Ph.D.  University of Maryland, College Park. 2009: 140 pages; 3359458.
3.
Late to Terminal Classic transition at Lamanai with implications for the Postclassic
by Pierce, Karen L., M.A.  University of Colorado at Denver. 2016: 479 pages; 10149341.
4.
Efficient ray tracing architectures
by Spjut, Josef Bo, Ph.D.  The University of Utah. 2015: 129 pages; 3727095.
6.
Architecting emerging memory technologies for energy-efficient computing in modern processors
by Jianxing, Wang, Ph.D.  National University of Singapore (Singapore). 2015: 161 pages; 10006096.
8.
Architectural support for efficient on-chip parallel execution
by Brown, Jeffery Alan, Ph.D.  University of California, San Diego. 2010: 159 pages; 3402089.
9.
Polymorphic chip multiprocessor architecture
by Solomatnikov, Alexandre, Ph.D.  Stanford University. 2009: 167 pages; 3343960.
10.
Smart memories: A reconfigurable memory system architecture
by Firoozshahian, Amin, Ph.D.  Stanford University. 2009: 196 pages; 3343953.
11.
Hardware Transactional Memory: A Systems Perspective
by Rossbach, Christopher John, Ph.D.  The University of Texas at Austin. 2009: 204 pages; 3434949.
12.
Domical: A new cooperative caching framework for streaming media in wireless home networks
by Shayandeh, Shahin, Ph.D.  University of Southern California. 2010: 125 pages; 3403757.
13.
Intelligent cache management techniques for reducing memory systemwaste
by Khan, Samira M., Ph.D.  The University of Texas at San Antonio. 2012: 109 pages; 3527415.
14.
Cooperative design, cooperative science: Investigating collaborative research through design with floracaching
by Bowser, Anne Elizabeth, Ph.D.  University of Maryland, College Park. 2016: 248 pages; 10129884.
15.
Building Scalable Architectures Using Emerging Memory Technologies
by Korgaonkar, Kunal Kishore, Ph.D.  University of California, San Diego. 2019: 121 pages; 13882185.
16.
Interacting effects of predation and competition in the field and in theory
by Sommers, Pacifica, Ph.D.  The University of Arizona. 2016: 128 pages; 10007216.
17.
Directory Storage Efficiency Improvement for Chip-Multiprocessors
by Shu, Wei, Ph.D.  University of Louisiana at Lafayette. 2018: 120 pages; 13420085.
19.
Productive Design of Extensible On-Chip Memory Hierarchies
by Cook, Henry Michael, Ph.D.  University of California, Berkeley. 2016: 153 pages; 10150942.
20.
21.
Modeling and design of high-performance and power-efficient 3D dram architectures
by Chen, Ke, Ph.D.  University of Notre Dame. 2013: 151 pages; 3732210.
22.
Security and Privacy Challenges in Content-Centric Networks
by Wood, Christopher A., Ph.D.  University of California, Irvine. 2017: 337 pages; 10684217.
23.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
24.
Spatio-termporal reasoning about agent behavior
by Shakarian, Paulo, Ph.D.  University of Maryland, College Park. 2011: 649 pages; 3461587.
25.
SRAM reliability improvement using ECC and circuit techniques
by McCartney, Mark P., Ph.D.  Carnegie Mellon University. 2014: 131 pages; 3733956.
26.
Parallelism and error reduction in a high performance environment
by Castaldo, Anthony M., Ph.D.  The University of Texas at San Antonio. 2010: 117 pages; 3433204.
27.
Architectures for transactional memory
by McDonald, Austen, Ph.D.  Stanford University. 2009: 143 pages; 3364506.
28.
Animacy, Symbolism, and Feathers from Mantle's Cave, Colorado
by Sommer, Caitlin Ariel, M.A.  University of Colorado at Boulder. 2013: 256 pages; 1539391.
29.
Dynamic Documents for Data Analytic Science
by Becker, Gabriel, Ph.D.  University of California, Davis. 2014: 189 pages; 3685178.
30.
Opportunities for near data computing in MapReduce workloads
by Pugsley, Seth Hintze, Ph.D.  The University of Utah. 2015: 98 pages; 3704952.
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