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1.
64-bit area efficient binary adder in quantum-dot cellular automata
by Gudala, Niharika, M.S.  California State University, Long Beach. 2016: 60 pages; 10108192.
2.
High-speed carry skip adder implemented using speculative Han-Carlson parallel prefix adder
by Narayanaswamy, Rakesh, M.S.  California State University, Long Beach. 2016: 45 pages; 10007410.
3.
Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate
by Midde, Bharath Reddy, M.S.  California State University, Long Beach. 2016: 59 pages; 10099864.
4.
Determining Optimal Arithmetic Circuits for Solving Linear Optimization Problems with SAT Solvers
by Nain, Prerna, M.S.  California State University, Long Beach. 2018: 54 pages; 10752239.
5.
Designing Framework for the Computer Aided Design of Silicon Carbide JFET Circuits in BLEO Environments
by Naidugari, Venkata Vinay, M.S.  The University of Mississippi. 2017: 104 pages; 10280107.
6.
Reverse converter design based on the New Chinese Remainder Theorem II using parallel prefix adders
by Sidda, Aditya, M.S.  California State University, Long Beach. 2016: 76 pages; 10182140.
7.
Algorithms and hardware designs for decimal multiplication
by Erle, Mark A., Ph.D.  Lehigh University. 2009: 229 pages; 3344791.
8.
Dynamic Load-Based Power and Clock Gating Techniques for High-Speed Digital Circuits
by Farah, Salim, Ph.D.  University of Louisiana at Lafayette. 2014: 128 pages; 3622218.
9.
Complexity and power consumption in stochastic iterative decoders
by Payak, Keyur M., M.S.  Utah State University. 2010: 52 pages; 1483787.
10.
Design of aging-aware variable-latency multiplier based on adaptive hold logic
by Pabbati Reddy, Sreeram Reddy, M.S.  California State University, Long Beach. 2016: 50 pages; 1606098.
11.
Modulo Multipliers with Adaptive Delay for a High Dynamic Range Residue Number System Using Booth Encoding
by Reddy, Ginni Sumanth, M.S.  California State University, Long Beach. 2017: 47 pages; 10263534.
12.
Fast modular exponentiation using residue domain representation: A hardware implementation and analysis
by Nguyen, Christopher Dinh, M.S.  University of Maryland, Baltimore County. 2013: 129 pages; 1551346.
13.
Design of a low power asynchronous Viterbi decoder for wireless communications
by Deshpande, Parikshit, M.S.  California State University, Long Beach. 2016: 47 pages; 10142986.
14.
An optimized modified booth recoder for efficient design of the add-multiply operator
by Mehta, Kunal, M.S.  California State University, Long Beach. 2015: 35 pages; 1603343.
15.
Quantum Circuit Synthesis using Group Decomposition and Hilbert Spaces
by Saraivanov, Michael S., M.S.  Portland State University. 2013: 164 pages; 1542568.
16.
Design Considerations for Nano-Electromechanical Relay Circuits
by Spencer, Matthew Edmund, Ph.D.  University of California, Berkeley. 2015: 102 pages; 3733438.
17.
Performance enhancement of a multiprecision multiplier by a dynamic voltage scaling and multiprecision operands scheduling
by Bugata Venkata Phani Srirama, Kalyan Chakravarthy, M.S.  California State University, Long Beach. 2016: 38 pages; 10111181.
18.
Improvement of a propagation delay model for CMOS digital logic circuits
by Stamness, Rodger Lawrence, M.S.  San Jose State University. 2010: 100 pages; 1477363.
20.
Energy-Efficient Architectures Based on STT-MRAM
by Guo, Xiaochen, Ph.D.  University of Rochester. 2015: 150 pages; 3723260.
21.
A 100 MHz 6th Order Continuous Time Band-Pass Sigma Delta Modulator with Active Inductor Resonators
by Dobson, Kevin, Ph.D.  The George Washington University. 2016: 115 pages; 10085732.
22.
System level methodology for low cost performance characterization of analog and mixed -signal circuits
by Park, Joon Sung, Ph.D.  The University of Texas at Austin. 2009: 149 pages; 3372676.
23.
Architectures for cryptography accelerators
by Cohen, Aaron Ethan, Ph.D.  University of Minnesota. 2007: 199 pages; 3277590.
24.
Composition Semantics of the Rosetta Specification Language
by Peck, Megan E., M.S.  University of Kansas. 2012: 100 pages; 1519367.
25.
An efficient architecture for adaptive finite impulse response filters on field programmable gate arrays
by Nallani Chakravartula, Krishna Chaitanya, M.S.  California State University, Long Beach. 2016: 56 pages; 10137445.
26.
Toward Adaptation and Reuse of Advanced Robotic Algorithms
by Baker, Christopher R., Ph.D.  Carnegie Mellon University. 2011: 199 pages; 3515709.
27.
Superconducting logic circuits operating with reciprocal magnetic flux quanta
by Oberg, Oliver Timothy, Ph.D.  University of Maryland, College Park. 2011: 337 pages; 3495583.
28.
64-bit high efficiency binary comparator in quantum-dot cellular automata
by Patalay, Dinkar, M.S.  California State University, Long Beach. 2016: 49 pages; 10111200.
29.
Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA's
by Pathanjali, Nandini, M.S.  University of Cincinnati. 2002: 110 pages; 10857176.
30.
Modification of an asynchronous dexterous hand movement decoder for hardware implementation
by Bosen, Adam Kevin, M.S.  Rochester Institute of Technology. 2010: 72 pages; 1480273.
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