Increasingly sensors for biological applications are implemented using mixed signal CMOS technologies. As feature sizes in modern technologies decrease with each generation, the power supply voltage also decreases, but the intrinsic noise level increases or remains the same. The performance of any sensor is quantified by the weakest detectable signal, and noise limits the ability of a sensor to detect the signal. In order to explore the trade-offs among incoming signal, the intrinsic physical noise of the circuit, and the available power resources, we apply basic concepts from information theory to CMOS circuits. In this work the circuits are modeled as communication channels with additive colored Gaussian noise and the signal transfer characteristics and noise properties are used to determine the classical Shannon capacity of the system. The waterfilling algorithm is applied to these circuits to obtain the information rate and the bit energy is subsequently calculated.
In this dissertation we restricted our attention to operational transconductance amplifiers, a basic building block for many circuits and sensors and oftentimes a major source of noise in a sensor system. It is shown that for typical amplifiers the maximum information rate occurs at bandwidths above the dominant pole of the amplifier where the intrinsic physical circuit noise is diminished, but at the same time the output signal is attenuated. Thus these techniques suggest a methodology for the optimal use of the amplifier, but in many cases it is not practical to use an amplifier in this manner, that is at frequencies above its 3dB cutoff. Further, a direct consequence of applying the classic waterfilling algorithm leads to the idea of using modulation techniques to optimize system performance by shifting signals internally to higher frequencies, providing a practical means to achieve the information rates predicted by waterfilling and at the same time maintaining the real world application of these amplifiers. In addition, the information rates and bit energy for basic CMOS amplifier configurations are studied and compared across configurations and processes. Further the additional design constraints formed by adding the information rate and the bit energy to traditional design characteristics is explored.
|Commitee:||Horiuchi, Timothy, Narayan, Prakash, Peckerar, Martin, Sandborn, Peter|
|School:||University of Maryland, College Park|
|School Location:||United States -- Maryland|
|Source:||DAI-B 73/03, Dissertation Abstracts International|
|Keywords:||Amplifiers, Cmos circuits, Noise, Power efficiency|
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