The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PDF) testing as techniques to structurally detect gross timing defects in modern integrated circuits (ICs). As effective as delay fault testing is for detecting such defects, as process technology continues to reach the ultra-deep sub-micron scale, interconnect parasitic effects have been playing a more integral role. However, these effects are context sensitive and will impact chip performance only under certain states. Current automatic test pattern generation (ATPG) tools are not aware of the context of the patterns and the performance impact that these at-speed test patterns will have on the chip during test. As a result, test escapes may occur since paths can be activated functionally that create excessive noise and critical failures in the field while it had already passed at-speed manufacturing tests. In this work, we propose novel techniques to generate patterns that are signal integrity-aware. By considering the locality of switching activity during pattern generation, both IR-drop and crosstalk can be leveraged to change the chip performance during test. Including these enhancements during pattern generation will produce more robust pattern sets that will increase defect coverage, assist in first silicon validation and debug, and improve device reliability in the field. In addition, a new model for estimating the switching activity during ATPG is presented to avoid the time consuming process of logic simulation and can be used to improve the performance of the proposed signal integrity-aware pattern generation. Also, a technique to avoid functionally untestable states is presented to maintain behavior during test that is closer to functional. This can be utilized in conjunction with the proposed pattern generation methodologies to prevent overtesting while still reaching the functional limits of the design.
|School:||University of Connecticut|
|School Location:||United States -- Connecticut|
|Source:||DAI-B 73/02, Dissertation Abstracts International|
|Keywords:||Delay faults, Fault testing, Pattern generation, Power-aware testing|
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