Historically, manufacturing defects (permanent physical damages) in the fabric have been the main concern for reliability in the configuration SRAMs of FPGA. For sub-100 nm regime, the dominant SRAM reliability concerns can be broadly categorized as soft errors and parametric yield failure. In the thesis, the impact of CAD tools on the reliability of the configuration SRAMs against soft errors and parametric failures has been studied.
In the first step, the challenges of enhancing the reliability of FPGA against soft errors in physical design is explained when no redundancy can be entertained, due to tight performance/area constraints. A novel solution is proposed which incorporates the soft error awareness in the routing and it is shown that without any compromise in the aforementioned parameters the failure rate of the design is improved by 15%.
In the next step, TMR (Triple Modular Redundancy) is employed to address soft errors. TMR has been widely used to remedy soft errors. However, recently it has been shown that TMR is not 100% soft-error proof in SRAM-based FPGAs, since soft errors might inject multiple faults which undermine the TMR integrity. Such faults are analyzed and then the redundancy-based soft error aware CAD flow is proposed; from the conception of the design to the physical design and synthesis. The main advantages are simultaneously reducing the TMR breaches as well better performance and area, when compared to the techniques which employ TMR in physical design.
In the rest of the thesis, the impact/challenges of applying parametric failure awareness in physical level and system level are extensively studied. As parametric failures are strongly related to the supply voltage of the SRAM, novel system level techniques are introduced which handle parametric failures while aggressive voltage scaling is performed on the SRAMs. Also, the impact of parametric failures is analyzed and remedied in placement as well.
In summary, this thesis has opened in new horizon in reliability-aware design for SRAM-based FPGAs. Rather than relying on device level, circuit level or architecture level solution to address reliability of SRAMs, I motivate the use of FPGA CAD tools for reliability enhancement.
|Commitee:||Givargis, Tony, Harris, Ian|
|School:||University of California, Irvine|
|Department:||Information and Computer Science - Ph.D.|
|School Location:||United States -- California|
|Source:||DAI-B 73/02, Dissertation Abstracts International|
|Subjects:||Computer Engineering, Computer science|
|Keywords:||Computer aided design, Fpga, Reliable CAD tools, Sram|
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