In a computing era of thousands of devices, many designs are developed to optimize memory management to allow larger amounts of fast memory access. Mobile devices such as phones, PDAs, MP3 audio players, and laptops are emphasizing performance and power savings. Cache power in an embedded processor can consume as much as 50% of the processor's power, where 17% of the cache power is derived from the Translation Lookaside Buffer (TLB). The TLB frequently performs virtual-address to physical-address translations that consume a large amount of power due to the memory components storing the translations.
Modifying the Bank Associative TLB to include small, filter banks along with a victim bank reduces the miss rate to the larger main TLB and effectively increases power performance This method reduces the filter bank associative TLB miss rates and accesses to the main TLB that will result in a power optimized TLB solution.
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 50/01M, Masters Abstracts International|
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