Dissertation/Thesis Abstract

Novel fast locking digital phase locked loop: Behavioral modeling and simulations using VHDL-AMS
by Nannaka, Anurag, M.S., California State University, Long Beach, 2010, 84; 1490320
Abstract (Summary)

A novel successive approximation fast locking digital phase lock loop (SAR DPLL) is presented and behaviorally modeled using VHDL-AMS. The DPLL operation includes two stages: (1) a novel course tuning stage which employs a successive approximation algorithm which is similar to the algorithm employed in SAR analog-to-digital converters (ADCs) and (2) a fine tuning stage which is similar to conventional DPLLs. The coarse tuning stage includes a frequency comparator, a successive approximation register, a digital-to-analog converter (DAC) and control logic.

A novel flash digital phase lock loop is also behaviorally modeled and presented. The coarse tuning stage includes a frequency comparator array, encoder and digital-to-analog converter. Lock time comparison between successive approximation, flash and conventional DPLL is performed to demonstrate the fast locking. The entire design is performed using Ansoft Simplorer.

Indexing (document details)
Advisor: Wagdy, Mahmoud
School: California State University, Long Beach
School Location: United States -- California
Source: MAI 49/04M, Masters Abstracts International
Subjects: Electrical engineering
Publication Number: 1490320
ISBN: 978-1-124-54607-0
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