Soft errors are intermittent malfunctions of hardware that are not reproducible. They may affect the data integrity and affect the system operation. These errors are growing reliability threat in VLSI system design. A soft error occurring in a memory cell or register is called a Single Event Upset (SEU).
Designs mapped into Field Programmable Gate Arrays (FGPAs) are more vulnerable to soft errors than ASIC implementations, due to the large number of configuration memory used to map the design into the FPGA. An SEU causes a unique failure mode in the mapped design due to the unique architecture of FPGAs.
In this work, we try to mitigate the effects of SEUs in SRAM based FPGAs. An SEU occurring in one of the configuration bits of the FPGA may cause a permanent error in the implemented circuit. Since the majority of FPGA real estate is dedicated for SRAM configuration bit, mitigating soft error in these configuration bits can improve the reliability of the mapped design. The goal of this work is the development of an SEU-aware placement and routing tool that is capable of producing an implementation that is less vulnerable to SEUs. To achieve this, we modified the cost function for the placement and the routing part of the VPR tool to reduce the effects of SEU in the final mapped design. The VPR tool is a general purpose FPGA placement and routing tool that is widely accepted and used in the academic field.
Two classes of errors that can be caused by an SEU in the routing resources were considered: switch open errors and switch short errors. During placement, we applied a cost function to estimate for the sensitivity to reduce the chances of the occurrence of these errors. We optimize for the switch open errors by minimizing the number of switches used for routing a net of the circuit. For reducing switch short errors, we try to minimize the overlapping area between nets. During routing, we carefully assign routing resources for the nets to minimize these errors. By using this approach we were able to reduce the number of total sensitive errors by 58% in average, but that reduction comes at the cost of increased critical path delay by on 54% on average.
|Advisor:||Tahoori, Mahdi B.|
|Commitee:||Kaeli, David R., Mi, Ningfang|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- Massachusetts|
|Source:||MAI 49/04M, Masters Abstracts International|
|Keywords:||FPGA placement, FPGA routing, Fault tolerance, SEU, SRAM FPGA, VPR|
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