Dissertation/Thesis Abstract

High-performance dram system design constraints and considerations
by Gross, Joseph, M.S., University of Maryland, College Park, 2010, 171; 1489105
Abstract (Summary)

The effects of a realistic memory system have not received much attention in recent decades. Often, the memory controller and DRAMs are modeled as a fixed-latency or random-latency system, which leads to simulations that are less accurate. As more cores are added to each die and CPU clock rates continue to outpace memory access times, the gap will only grow wider and simulation results will be less accurate.

This thesis proposes to look at the way a memory controller and DRAM system work and attempt to model them accurately in a simulator. It will use a simulated Alpha 21264 processor in conjunction with a full system simulator and memory system simulator. Various SPEC06 benchmarks are used to look at runtimes. The process of mapping a memory location to a physical location, the algorithm for choosing the ordering of commands to be sent to the DRAMs and the method of managing the row buffers are examined in detail. We find that the choice in these algorithms and policies can affect application runtime by up to 200% or more. It is also shown that energy use can vary by up to 300% by changing the address mapping policy. These results show that it is important to look at all the available policies to optimize the memory system for the type of workload that a machine will be running. No single policy is best for every application, so it is important to understand the interaction of the application and the memory system to improve performance and reduce the energy consumed.

Supplemental Files

Some files may require a special program or browser plug-in. More Information

Indexing (document details)
Advisor: Jacob, Bruce L.
Commitee: Qu, Gang, Yeung, Donald
School: University of Maryland, College Park
Department: Electrical Engineering
School Location: United States -- Maryland
Source: MAI 49/04M, Masters Abstracts International
Source Type: DISSERTATION
Subjects: Computer Engineering, Electrical engineering
Keywords: Ddr3, Dram, Memory controller, Power modeling, System simulation
Publication Number: 1489105
ISBN: 9781124484723
Copyright © 2019 ProQuest LLC. All rights reserved. Terms and Conditions Privacy Policy Cookie Policy
ProQuest