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Dissertation/Thesis Abstract

Self-Timed Circuits, Memories, and Power Electronics for High-Ripple Energy Harvesting Power Supplies
by Wenck, Justin A., Ph.D., University of California, Davis, 2010, 258; 3427486
Abstract (Summary)

Minimizing system volume while maximizing system lifetime is crucial for body area sensor network applications (BASNs), such as heart rate monitoring, drug delivery, and prosthetic actuation. Optimizing system lifetime and volume also benefits current wireless sensor network applications, such as tire pressure monitoring and building automation. Only by exploiting low-power circuit design, micro-scale energy harvesting, and optimal power electronics selection can system volume be minimized while allowing for potentially unlimited system lifetime.

This work explores the relationship between power supply quality, quantified by the supply ripple voltage, and passive component sizing for energy harvesting systems. Linear or switching regulators can reduce supply ripple, but passive power electronics, which power the load from a bypass capacitor following a rectifier or directly from an AC supply, can also provide usable supply rails. We will show that a reduced ripple voltage requires larger passive components and therefore a larger system volume. We present a simulation methodology to compare switching, linear, and passive power electronics architectures on the basis of system performance, power, and volume. This methodology is enabled by developing a load model that allows both performance and power to be simulated. This allows power electronics architectures to be compared by end user criteria, such as runtime, duty cycle, or average throughput, instead of just power consumption.

To enable a digital system to run from an AC, or high-ripple, power supply, memory techniques are developed for both 180 nm and 90 nm digital CMOS processes. A test chip demonstrating self-timing, power-on reset circuitry, and embedded dynamic memory for energy harvesting AC voltages has been designed in 180 nm CMOS. The measured DRAM retention time of 28 ms at 1.8 V ensures correct operation for AC supplies with frequencies below 60 Hz. The challenges and benefits of scaling to 90 nm CMOS are discussed, and three alternative DRAM cells are introduced and compared using post-layout simulations. Several design examples illustrate how retention time, write voltage, AC supply frequency, and bypass capacitance interact to create a complex design space. This leaves the designer with many options to create an autonomous, unlimited lifetime, energy harvesting system that meets performance and volume requirements for BASN applications.

Indexing (document details)
Advisor: Amirtharajah, Rajeevan
Commitee: Akella, Venkatesh, Hurst, Paul
School: University of California, Davis
Department: Electrical and Computer Engineering
School Location: United States -- California
Source: DAI-B 71/12, Dissertation Abstracts International
Subjects: Electrical engineering
Keywords: Energy harvesting, Low-power, Power electronics, Self-timed
Publication Number: 3427486
ISBN: 978-1-124-31945-2
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