The computation capability of the integrated chips has been elevated constantly as a result of aggressive technology scaling. However, as a companion, the heat dissipation of the high-performance chips keeps increasing, causing thermal variation in both temporal and spatial terms. The impact of temperature on integrated chips is multifaceted. High temperature degrades the reliability and increases the leakage power of the chips. Temperature also has a complex implication on circuit timing, introducing new challenges in the circuit synthesis and verification flow.
Resolving these thermal issues requires a comprehensive treatment across multiple design levels. In this dissertation, we propose such a multilevel treatment. The three key aspects of our treatment is monitoring, mitigation and utilization.
Thermal monitoring mechanisms constitute our system level approach, which plays an essential role for thermal emergency prediction, detection, and prevention. Accuracy is the essential goal for the design of the thermal monitoring system. We factorize the sources of the monitoring inaccuracy into three parts: (1) inaccuracy due to the placement of the sensing devices, (2) inaccuracy due to the routing infrastructure, and (3) inaccuracy due to the precision of the sensing devices. Correspondingly, we have proposed three design methodologies/concepts to diminish these three sources. These techniques include (1) non-uniform and uniform sensor placement strategies, (2) a sensor routing infrastructure which supports 4-wire (Kelvin) voltage measurement, and (3) an Integrated On-chip Thermocouple Array (IOTA).
Thermal mitigation is the microarchitecture level solution, which aims to resolve the thermal emergencies by effectively removing the heat out of the hotspots. To achieve efficient heat mitigation, we investigate on on-chip active cooling technology that employs miniature thermoelectric heat pumps. We indentify the design constraints and trade-offs for an on-chip thermoelectric cooling system. In order to examine the cooling system, we established a novel theoretical analysis framework which extends the theory of inverse-positive matrix and the eigenvalue/eigenvector theory in linear algebra. Built on this theoretical foundation, we propose a systematic optimization scheme to maximize the efficiency of the cooling system.
Thermal utilization is our RTL/gate level therapy, which exploits the temperature fluctuations in both temporal and spatial terms to guarantee timing closure. Instead of viewing temperature fluctuations as adverse effects, we treat temperature as a dimension of timing optimization and temperature dependent timing slacks as manageable resources. Our proposed utilization techniques include (1) a self-adjusting clock tree architecture (SACTA), and (2) a synergistic Vth assignment and clock skew scheduling technique.
|Advisor:||Memik, Seda Ogrenci|
|Commitee:||Dick, Robert, Grayson, Matthew, Ismail, Yehea, Memik, Seda, Zhou, Hai|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- Illinois|
|Source:||DAI-B 71/05, Dissertation Abstracts International|
|Keywords:||Algorithm, Integrated chips, Thermal mitigation, Thermal monitoring, Thermal optimization, Thermal utilization|
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