Dissertation/Thesis Abstract

A methodology to design pipelined simulated annealing kernel accelerators on space-borne Field-Programmable Gate Arrays
by Carver, Jeffrey Michael, M.S., Utah State University, 2009, 56; 1468984
Abstract (Summary)

Increased levels of science objectives expected from spacecraft systems necessitate the ability to carry out fast on-board autonomous mission planning and scheduling. Heterogeneous radiation-hardened Field Programmable Gate Arrays (FPGAs) with embedded multiplier and memory modules are well suited to support the acceleration of scheduling algorithms. A methodology to design circuits specifically to accelerate Simulated Annealing Kernels (SAKs) in event scheduling algorithms is shown. The main contribution of this thesis is the low complexity scoring calculation used for the heuristic mapping algorithm used to balance resource allocation across a coarse-grained pipelined data-path. The methodology was exercised over various kernels with different cost functions and problem sizes. These test cases were benchedmarked for execution time, resource usage, power, and energy on a Xilinx Virtex 4 LX QR 200 FPGA and a BAE RAD 750 microprocessor.

Indexing (document details)
Advisor: Dasu, Aravind
Commitee: Eames, Brandon, Spencer, Edmund A.
School: Utah State University
Department: Electrical and Computer
School Location: United States -- Utah
Source: MAI 48/01M, Masters Abstracts International
Subjects: Electrical engineering, Computer science
Keywords: Field programmable gate arrays, Mapping, Pipelined, Resource binding, Scheduling, Simulated annealing
Publication Number: 1468984
ISBN: 9781109334050
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