Dissertation/Thesis Abstract

Rapid laser crystallization of semiconductors for three-dimensional integration
by Witte, Daniel Jonathan, Ph.D., Stanford University, 2009, 177; 3364516
Abstract (Summary)

Three-dimensional (3D) integration of semiconductor devices can yield advantages in circuit density, power consumption, and speed over conventional integrated circuit (IC) technology in which all transistors are fabricated in one plane. 3D integration allows circuit functions to be split across multiple layers, which—for certain kinds of circuits—allows significant reductions in average wire length. Since wires are the dominant factor in determining logic delay, this can result in faster systems. Vertical interconnect densities of more than a million per square millimeter are critical to achieving this advantage, and to do this, a monolithic approach is required where circuit layers are fabricated sequentially on a single wafer.

The principal challenge is obtaining single-crystal, device-quality semiconductor material on upper circuit layers. We show that, beginning from an amorphous silicon film deposited at low temperature on an amorphous silicon dioxide substrate, a rapid laser crystallization process using a 532nm Nd:YAG laser can form preferentially oriented crystals with a <001> out-of-plane orientation. Strong orientation was achieved with pulse lengths 2ms and greater and with 200nm thick silicon films. By patterning the amorphous silicon film into neck structures prior to laser crystallization, a single <001> crystallite can be selected to seed a finger region 10pm in length and several microns wide. Carrier mobility in these crystals can be above 900 cm2/Vs for electrons and 250 cm2/Vs for holes, and is thus comparable to SOI reference material. These regions could be used for fabrication of devices, or as seed material for further crystallization. A technique such as rapid melt growth (RMG) of silicon or germanium could be used to crystallize device material and propagate the seed orientation over an entire die. Simulation shows that this could be done without damaging circuit layers underneath, by maintaining their temperature below 400°C. A reflective shield layer and a thermal isolation layer such as silicon dioxide several microns thick are required. The combination of preferentially oriented seed crystallization with an RMG approach would allow the fabrication of multiple circuit layers on a single wafer in a sequential, monolithic fashion.

Indexing (document details)
Advisor: Pease, R. Fabian W.
School: Stanford University
School Location: United States -- California
Source: DAI-B 70/07, Dissertation Abstracts International
Subjects: Electrical engineering
Keywords: Amorphous silicon, Annealing, Laser crystallization
Publication Number: 3364516
ISBN: 978-1-109-24309-3
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