Wireless sensor networks are an emerging and ever-expanding technology. Often, the applications which use wireless sensor networks are constrained by the slow processing power of the micro-controllers. This results in a decrease in bandwidth. Adding other forms of computation to the data stream such as encryption and compression make the situation worse.

This thesis explores the use of reprogrammable logic and synthesized hardware to overcome this bandwidth bottleneck. As a proof of concept a system has been created which can perform sensing, audio processing as well as communication. The system runs a ported version of MantisOS which supports multiple threads, a light weight low power[3] kernel as well as sensor networking routing protocols.

In the results section, a comparison is made between the timing for using software only, a single and multiple synthesized Fast Fourier Transform cores to perform an Fourier Transform.

As the amount of power consumption is of high importance in sensor networking, special attention to the power requirements for adding an FFT core as well as power differences between ASICs and FPGAs is considered. Additionally, several promising solutions for reducing the power threat of FPGAs is considered as well.