Reconfigurable computing (RC) systems are composed of nodes with tightly coupled microprocessor(s) and field programmable gate arrays (FPGA). These systems provide unique application acceleration opportunities through the reconfigurability of the FPGA co-processor, which enables the customization of the hardware to the underlying applications and the processing synergy between the microprocessor and the FPGA. A formal methodology for hardware-software co-design, however, has not yet been established for the mapping of applications onto such reconfigurable systems. To the best of our knowledge, this is the first effort to formalize application co-design on reconfigurable computing systems.
This research addresses the task of formalizing hardware-software co-scheduling for RC systems. Scheduling algorithms from related domains such as embedded computing (EC), heterogeneous computing (HC), and reconfigurable hardware (RH) were evaluated for their potential benefits to scheduling for RC. Selected algorithms from these domains were extended to provide scheduling capabilities for RC systems. The enhanced algorithms are analytically and experimentally shown to provide over one order of magnitude improvement in application throughput.
The execution models of EC, HC, and RH, however, are quite different from that of RC systems and thus scheduling solutions were often not optimal. To address this, a formal co-design methodology and an efficient co-scheduling algorithm, Reconfigurable-Computing Co-Scheduling (ReCoS), has been proposed. The co-design methodology proposes a framework to identify an optimal co-schedule based on the available resources, constraints, and performance targets. The ReCoS algorithm is shown to provide up to one order of magnitude improvement over the enhanced scheduling algorithms from related domains for mapping applications onto an RC system.
The proposed algorithms can be used by Hardware-Software compilers to deliver optimized solutions. They can also be used as the foundation for productivity tools that can guide users in Hardware-Software co-design of RC applications. To increase the usability and decrease the time necessary to co-design an application for an RC system, The Center for High-Performance Reconfigurable Computing (CHREC) Performance Analysis and Co-Design Tool (CHREC-PACT) was created. PACT provides application performance analysis, resource utilization, constraint analysis, and co-design assistance tools to quickly identify an optimal co-schedule between the microprocessor and its reconfigurable processor.
|Commitee:||Ahmadi, Shahrokh, Della Torre, Edward, Eom, Kie-Bum, Gonzalez, Ivan, Korman, Can E.|
|School:||The George Washington University|
|School Location:||United States -- District of Columbia|
|Source:||DAI-B 69/02, Dissertation Abstracts International|
|Keywords:||Coscheduling, FPGAs, Hardware design, Reconfigurable computing, Software design|
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