Miniaturization in Electronics does not result in smaller high-performance chips, but in similar size chips with exponentially higher complexity---more devices and more complex wiring. An electronic chip is only as good as its wiring. Today, copper interconnect wires are increasingly becoming performance bottlenecks in integrated circuits. Copper was introduced by chip makers in the late 90's to replace aluminum when the aluminum wires started to limit chip performances, marking the beginning of the "interconnect-centric era". What material is next beyond copper? Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. This dissertation builds on these modeling promises, and explores the use of CNT interconnects from an experimental point of view. As a proof of concept, this work culminates in the realization of the first digital integrated circuit with CNT interconnects and silicon CMOS transistors.
The focus of this dissertation is on local horizontal interconnects---the wires connecting nearby logic gates which are routed with the tightest pitch and highest density. In state-of-the-art integrated circuits, the narrowest wires have entered the nanoscale regime with wires narrower than 100 nm. As copper wires are scaled down to such narrow dimensions to keep up with the miniaturization of the transistors according to Moore's Law, they suffer from adverse narrow-width effects degrading the chip performance. In the short term, advances in copper wire fabrication will alleviate these problems. In the long term, the introduction of another interconnect material as a replacement for copper might be the solution. In this context, CNTs offer great promises as alternative interconnect materials. This dissertation reviews first the issues plaguing nanoscale copper interconnects, and then the system-level incentives for using CNT interconnects.
This dissertation aims at demonstrating that CNTs can effectively be used as interconnects in a CMOS integrated circuit. As there is no established infrastructure or method for building an integrated circuit with CNT interconnects, our approach was to start from raw commercially-available CNT materials, develop and implement our own CMOS integration scheme.
Based on previous art, we developed a method to fabricate arrays of CNT interconnects at low temperature suitable for CMOS co-integration. We then extensively characterized electrically the CNTs to understand their properties as interconnect wires. The CNT interconnects were then integrated with a circuit fabricated in a 0.25-μm CMOS technology. We designed this CMOS circuit as a vehicle to demonstrate the feasibility of CNT interconnects. This prototype chip, running above 1 GHz, also served as a platform to assess the performances of CNT interconnects in a realistic digital integrated circuit environment. Using this platform, we evaluated local interconnects (14 μm in length, 30 nm in diameter) made of an individual multi-wall CNT (MWCNT). We experimentally extracted the sub-ns delay of these wires to benchmark their future potential for the first time. Furthermore, we compared our experimental results with an existing MWCNT interconnect model, and discussed the origin of discrepancies.
There remain formidable challenges before a competitive CNT interconnect technology can be implemented. However, our prototype chip sets a milestone by operating above 1 GHz, paving the way for future multi-GHz nanoelectronics based on the use of CNTs.
|Advisor:||Wong, H.-S. Philip, Lee, Thomas, Saraswat, Krishna|
|School Location:||United States -- California|
|Source:||DAI-B 69/05, Dissertation Abstracts International|
|Keywords:||CMOS, Carbon nanotubes, Integrated circuits, Interconnects|
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