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Dissertation/Thesis Abstract

Development of Graphene Synthesis and Characterization Techniques Toward CMOS Applications and Beyond
by Zietz, Otto Kno, Ph.D., Portland State University, 2021, 104; 28262446
Abstract (Summary)

Graphene exhibits mechanical and electrical properties which, coupled with its two dimensional (2D) morphology, make it an attractive material component for inclusion in a wide range of industries. Since the discovery of graphene in 2004, industry adoption has been limited due to the demanding synthesis requirements for high quality and connected graphene as well as the difficulties associated with direct incorporation. Chemical vapor deposition (CVD) has emerged as the most cost efficient method for producing high quality graphene at scales suitable for mass production. However, the 1000°C temperatures and micrometer thick catalysts required for this process preclude direct inclusion in applications with topographically varied surfaces as graphene is produced in planar sheets that must be transferred.

One attractive application for graphene is as a diffusion barrier in CMOS applications as the single atom thick material has shown significant ability to block copper diffusion at elevated temperatures. For realization of this application, both the required catalyst thicknesses and synthesis temperatures for graphene production must be reduced to enable direct graphene incorporation on these nanoscale and nonplanar surfaces without thermal damage to existing components. A second application in which graphene inclusion would be beneficial is the field of spintronics, in which the spin orientation of electrons are used as an additional degree of freedom for computation and information storage. This beyond-CMOS application represents an avenue for significant improvement over current technologies and graphene, with its weak spin orbit coupling and high electron mobility, displays potential as a long-distance spin transport component of future spintronic devices. Characterization of graphene’s spin transport properties has been primarily investigated in a nonlocal spin valve device (NLSV), resulting in experimental spin transport parameters orders of magnitude below those theoretical predicted. To advance graphene as a component for future spintronic applications, new device designs to explore spin transport phenomena not detectable in NLSV devices as well as scalable fabrication techniques will be needed.

In this work, we develop graphene synthesis techniques to reduce required temperatures through hydrocarbon precursor control during plasma enhanced chemical vapor deposition (PECVD). Through manipulation of the size and ionization state of hydrocarbon precursors that interact with the growth catalyst, we demonstrate 95% few-to-monolayer graphene synthesis at 500°C on 50 nm catalysts, representing a 10-fold reduction in catalyst thickness requirements at temperatures approaching the limit for direct incorporation in CMOS applications. Additionally, we demonstrate manipulation of metal catalyst morphology and composition toward controlling graphene layer number, defect types, and uniformity. Characterization of trimetallic catalysts, compared to single metal or bimetallic catalysts traditionally examined in literature, reveal that low temperature graphene synthesis pathways can be manipulated through small additions of less reactive metals (Gold and Copper) to primarily high reactivity metal catalysts (Ni) through both energetic and surface modulation resulting in monolayer graphene synthesis.

While low temperature graphene synthesis techniques are needed for graphene incorporation in current CMOS products, beyond-CMOS applications do not necessarily require temperature restrictions on synthesis as fabrication of these devices can implement planar graphene as the first device component. To characterize graphene as a spin transport channel, commercially available graphene grown at elevated temperatures is used to address spin transport properties through design of a novel device configuration, the hybrid drift diffusion spin valve (HDDSV), in which an additional transport channel is added to the standard NLSV. This device architecture has not been previously studied and is aimed at revealing magnetic contact effects on graphene spin transport as well as exploring drift and diffusion interactions with respect to achievable spin signals. Wafer scale fabrication of these devices is demonstrated and processing techniques are optimized to enable spin signal detection on arrays containing 120 individual devices. Characterization of the new HDDSV configuration reveals changes to detected spin signals in both the standard NLSV portion and the added channel, revealing spin signals as large as 865Ω in the additional transport channel compared to an average signal of 7.3Ω in the traditional configuration. The additional channels also exhibit detectable spin signal under a 3 point local measurement, representing a potential avenue toward long distance spin transport and enabling increased device complexity that will be necessary for the realization of graphene based spintronic devices.

These findings represent the development of graphene synthesis and characterization techniques aimed at advancing fundamental understanding and enabling further practical application. The methods developed in this study serve as new avenues for continued improvement toward direct incorporation of a material that has the potential to revolutionize a number of fields.

Indexing (document details)
Advisor: Jiao, Jun
Commitee: Lee, Tae-Kyu, Chen, Zhiqiang, Schumacher, Thomas
School: Portland State University
Department: Mechanical Engineering
School Location: United States -- Oregon
Source: DAI-B 82/9(E), Dissertation Abstracts International
Source Type: DISSERTATION
Subjects: Materials science, Physics, Mechanical engineering
Keywords: Chemical vapor deposition, Graphene synthesis, Spintronics, Complementary Metal-Oxide Semiconductor
Publication Number: 28262446
ISBN: 9798597050331
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