As big data processing and cloud computing continue to grow exponentially, more than 85% of global data traffic has remained within data centers. A significant part of communication in datacenters, including rack-to-rack, rack-to-server, and building-to-building, is based on short-reach (850 nm, up to 500 m) and long haul (1310–1550 nm, up to 10 km) optical communication.
High-speed and high-efﬁciency photodiodes (PDs) play an important role in optical communication links. III-V-based optical transceivers could reach up to 25 Gb/s speed per channel. However, III-V-based photodiodes have not shown promising potential for monolithic optoelectronic integration via CMOS technology. Novel materials and techniques are needed to pave the way for monolithic integration of optical components with signal-processing electronics on a single silicon chip to reduce cost, energy consumption, and improve link efficiency.
We designed efficient micro/nanoholes light-trapping structures to overcome the low responsivity of silicon-based photodiodes. Higher optical absorption in an ultrathin active region of a photodiode provides us the opportunity to realize a high-speed and highly efficient photodiode for short-reach and long-haul optical communication.
The fabricated Si pin device exhibits an ultrafast impulse response (full-width at half-maximum) of 30 ps and a high efﬁciency of more than 50% quantum efficiency (responsivity more than 0.35 A/W) at 850 nm. Different passivation methods were applied to improve the surface damages/traps to reach low leakage less than 1 nA. A high-speed photodiode model consisting of an optical generation mechanism and equivalent circuit based on the measured DC/RF characterizations has been developed. The equivalent PD model is used in a comprehensive system simulation of an end-to-end optical link to evaluate the device in terms of bit error rate (BERT) and link power budget.
A transimpedance amplifier (TIA) and a 2-Tap Feed-Forward Equalizer (FFE) were designed and simulated based on the photodiode specifications to provide the optimum optoelectronics scheme for hermetic packaging. Comparing the experimental and simulation results, we explored design and fabrication challenges and offered solutions to reach the design targets.
A 10 Gb/s CMOS-compatible surface-illuminated Ge/Si photodiode integrated with photon-trapping microhole arrays with broadband, high efficiency up to 1700 nm is designed and fabricated. The Ge/Si photodiode has > 80% and > 73% EQE at 1310 nm and 1550 nm, respectively. The Ge/Si photodiode exhibited acceptable performance close to Ge bandgap, making it a promising candidate for the emerging technologies in the L-band communication window.
To move toward CMOS monolithic optoelectronic integration, a novel Metal-Semiconductor-Metal (MSM) PD with photon trapping structure was designed, fabricated, and characterized. The MSM device could reach more than 70% quantum efficiency (7-folds enhancement) at 850 nm while maintaining more than 10 Gb/s bit rate performance. The MSM structure offers practical solutions to most of the challenges experienced by a vertical pin PD. More importantly, the MSM structure has the potential to accommodate the CMOS foundry design rules check (DRC) flow.
A photodiode with microhole surface arrays integrated with a high-speed TIA is designed and simulated in SiPh BiCMOS technology platform. The design received the DRC approval from Tower Semiconductor foundry to be fabricated in their facilities.
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|Advisor:||Islam, M. Saif|
|Commitee:||Woodall, Jerry M., Gu, Q. Jane, Srinivasan, Vivek J.|
|School:||University of California, Davis|
|Department:||Electrical and Computer Engineering|
|School Location:||United States -- California|
|Source:||DAI-B 82/5(E), Dissertation Abstracts International|
|Subjects:||Electrical engineering, Biomedical engineering|
|Keywords:||High-speed, High-efficiency , CMOS-compatible photodiodes, Datacom interconnects|
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