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Dissertation/Thesis Abstract

Design of the Configuration and Readout Electronics for a Multi-Channel Integrated Circuit Used in the Detection and Monitoring of Ionizing Radiation
by Allipuram, SaiGeetha, M.S., Southern Illinois University at Edwardsville, 2019, 112; 13866159
Abstract (Summary)

This thesis describes the design of the configuration and readout electronics for a multi-channel integrated circuit (IC) which is used in the detection and monitoring of ionizing radiation in low- and intermediate-energy nuclear physics experiments. The sixteen channel chip discussed in this thesis can be used in a wide variety of nuclear physics applications and is suitable for use whenever silicon strip detectors are employed.

The chip can be used to determine the energy of a charged particle striking the detector, as well as, the the time interval between the arrival of the particle at the detector and an externally supplied time reference. The configuration and readout circuits, common to all of the sixteen signal processing channels, as well as the digital logic contained within a single signal processing channel, was implemented using the Verilog Hardware Description Language (HDL) and a 0.35 um standard cell library. Moreover, the IC christened HINP5 (Heavy Ion Nuclear Physics chip - Version 5), will be fabricated using the AMS (Austrian Microsystems) 0.35 um CMOS process in the Fall of 2019.

The IC is congured via three 8-bit conguration registers. Moreover, each channel contains a 6-bit Digital-to-Analog Converter (DAC) which must be programmed to set a threshold used by the Constant Fraction Discriminator (CFD), located in the timing branch within each channel. The IC supports data sparsication where a channel automatically resets itself (after a programmable delay time) unless explicitly directed to enter readout mode by an externally generated control signal.

The Verilog-driven design described in this thesis was implemented using Cadence's EDI (Encounter Digital Implementation) tools for synthesis and place n' route. The standard cell designs were then imported into Cadence's Virtuoso custom IC tools and validated at the electrical level. The use of the a standard cell approach greatly reduced design time and allows for changes to be made easily to the readout and configuration logic.

Indexing (document details)
Advisor: George, Engel L.
Commitee: Noble, Bradley, York, Timothy
School: Southern Illinois University at Edwardsville
Department: Electrical Engineering
School Location: United States -- Illinois
Source: MAI 58/06M(E), Masters Abstracts International
Subjects: Electrical engineering
Publication Number: 13866159
ISBN: 978-1-392-25967-2
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