COMING SOON! PQDT Open is getting a new home!

ProQuest Open Access Dissertations & Theses will remain freely available as part of a new and enhanced search experience at

Questions? Please refer to this FAQ.

Dissertation/Thesis Abstract

Design and Analysis of the Linear Branch of an Integrated Circuit for Use in Nuclear Physics Experiments Employing Si-Strip Detectors
by Korkmaz, Anil, M.S., Southern Illinois University at Edwardsville, 2019, 93; 13858244
Abstract (Summary)

This thesis describes the design of the linear branch of a signal processing channel which will be part of a multi-channel integrated circuit for use in radiation monitoring. The thesis describes the design of a charge amplifier, a Gaussian filter, and a peak sampling circuit. The IC is expected to be fabricated through in Fall 2019. The IC has been named HINP5 (Heavy Ion Nuclear Physics IC–Version 5). The design presented here was implemented using a 0.35 μm AMS (Austrian Micro-Systems) CMOS process.

The charge amplifier consists of a very low-noise, high dynamic range two-stage OTA (GBW in excess of 130 MHz) and three double-poly capacitors, each shunted by a small pseudo-resistor (used for pole-zero cancellation) realized using just a few small FETs, thereby greatly reducing silicon area. The charge amplifier has dual outputs, each of which connect to the input of a Gaussian filter used for signal shaping.

The respective charge gain for the two sub-channels is X1 (low-gain) and X4 (high-gain). The use of dual outputs significantly relaxes the noise and dynamic range requirements of the shaper and peak sampling circuits which follow and allows us to achieve outstanding energy resolution (lower than 25 keV–FWHM) for the high-gain output while maintaining a highly linear response for energies as large as 400 MeV in the “low-gain” sub-channel. The outputs from both sub-channels is brought out of the chip differentially and then sampled by off-chip ADCs.

The peak sampler is composed of an OTA (Operational Transconductance Amplifier) along with a diode-connected NFET and a sampling capacitor. The circuit makes use of correlated double sampling (CDS) to dramatically reduce the output 1/f noise and DC offset associated with the use of small transistors.

Indexing (document details)
Advisor: Engel, George L.
Commitee: Noble, Bradley, York, Timothy
School: Southern Illinois University at Edwardsville
Department: Electrical Engineering
School Location: United States -- Illinois
Source: MAI 58/06M(E), Masters Abstracts International
Subjects: Engineering, Electrical engineering
Publication Number: 13858244
ISBN: 978-1-392-26352-5
Copyright © 2021 ProQuest LLC. All rights reserved. Terms and Conditions Privacy Policy Cookie Policy