Architecting a cache-coherent memory hierarchy for computer processor is challenging for scaled up CMPs. This dissertation investigates two approaches to efficiently support directory based cache-coherent memory for processors.
The first approach is dubbed Non-U niform Directory Architec-ture (NUDA) framework aiming at CMP scalability improvement by drastically reducing on-chip directory area overhead. Exploiting our newly observed insights, NUDA employs a multi-level directory conguration in CMP, equipping a small on-chip buer to keep only "active" Directory Vectors (DVs) for sustained execution performance.
This dissertation also investigated an efficient on-chip CMP directory design that is featured with relinquishment coherence and compressed sharer tracking (ReCoST) for superior directory storage eciency, aiming to address the shortcomings of excessive directory area overhead. By dropping long runs of zeros in present-bit vectors (PVs) and storing distinct PVs in a sharer pattern table (SPT), directory storage overhead is reduced. In addition, relinquishment coherence is adopted to boost SPT utilization by transforming a PV to its variations, ensuring exact sharer tracking. ReCoST requires no over ow provision, as a result of its unique relinquishment coherence approach.
|Commitee:||Amini, Morsen, Chen, Sheng, Farmer-Kaiser, Mary, Kumar, Ashok, Totaro, Micheal W.|
|School:||University of Louisiana at Lafayette|
|School Location:||United States -- Louisiana|
|Source:||DAI-B 80/08(E), Dissertation Abstracts International|
|Subjects:||Computer Engineering, Engineering|
|Keywords:||Chip-multiprocessors, Directory storage efficiency improvement|
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