It is well known that CMOS scaling trends are now accompanied by less desirable byproducts such as increased energy dissipation. To combat the aforementioned challenges, solutions are sought at both the device and architectural levels. With this context, this work focuses on developing a systematic circuit design methodology for Nanomagnet Logic (NML) devices, and exploring the benefits of utilizing beyond-CMOS emerging transistors to process information with the non-binary/non-von Neumann computer architecture of Cellular Neural Networks (CNNs).
Nanomagnet Logic (NML) is a device architecture that performs logic operations through fringing field interactions between nano-scale magnets. The design space for NML circuits is large and so far there exists no systematic approach for determining the parameter values (e.g., device-to-device spacings, clocking field strength etc.) to generate a predictable design solution. This work presents a formal methodology for designing NML circuits that marshals the design parameters to generate a layout that is guaranteed to evolve correctly in time at 0K. The approach is further augmented to identify functional design targets when considering thermal noise associated with higher temperatures.
A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. This work shows that emerging technologies like tunneling field effect transistors (TFETs) can be successfully employed in CNNs to solve binary classification problems. Such systems provide significant power savings when compared to the conventional resistor-based CNN. Moreover, TFET-based CNN reduces implementation footprints by eliminating the hardware required to realize output transfer functions.
It is also shown how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. CNNs based on devices such as graphene transistors – with multiple steep current growth regions separated by negative differential resistance (NDR) in their I-V characteristics – could be used to recognize multiple patterns simultaneously, (This would require multiple steps given a conventional, binary CNN.) Also, a circuit built from TFETs is used in CNN to perform similar tasks. With this approach, more “exotic” device I-V characteristics are not required – which should be an asset when considering issues such as cell-to-cell mismatch, etc. As a case study, a CNN-cell design is presented that employs TFET-based circuitry to realize ternary outputs, and employed to efficiently solve a tactile sensing problem. The total number of computation steps as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN.
Much existing work reports energy dissipation for CNNs at the chip level, which includes dissipation of sensors, actuators, and other components. As such, the impacts of various system variables, e.g., application templates, characteristics of the resistive element, etc., on the energy profile of a CNN cannot be easily determined. This work also proposes analytical models to estimate CNN power and performance. Power dissipations, and settling times obtained via the models for different linear, and non-linear characteristics are verified through circuit simulation. Simulation results show that the proposed models predict power dissipation and settling time with less than 1% and 3% errors, respectively. Case studies are performed by using these models, for a tactile sensing problem, and a pattern recognition problem to compare power and performance between tunneling field effect transistor (TFET) based non-linear CNN and conventional linear resistor based CNN.
Traditional, CMOS based, von Neumann architectures face daunting challenges in performing complex computational tasks at high speed and with low power on spatio-temporal data, e.g., image processing, pattern recognition, etc. This work studies the potential of analog/mixed-signal information processing using TFETs in the context of cellular neural networks (CNNs). A TFET-based, mixed signal CNN architectures for spatio-temporal information processing is presented. Assuming a 14 nm InAs Homojunction TFET for the proposed architecture, power efficiency of more than 2,000 GOPS/W is projected for a number of different CNN templates. By comparison, state-of-the-art hardware assuming CMOS technology promises a power efficiency only close to 1,000 GOPS/W.
|School:||University of Notre Dame|
|Department:||Computer Science and Engineering|
|School Location:||United States -- Indiana|
|Source:||DAI-B 80/06(E), Dissertation Abstracts International|
|Subjects:||Computer Engineering, Electrical engineering, Computer science|
|Keywords:||Architecure, Cellular neural networks, Neural networks, Performance modeling, Power modeling, Tunneling fet|
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