This thesis presents the design and simulation of a multi-channel integrated circuit (IC) that will be used in nuclear physics experiments. The chip is being designed as a companion chip for another IC used in particle identification called PSD8C. The IC described in this thesis is used to create precise timing pulses for starting time-to-voltage converters (TVCs) and gated integrators on the PSD8C. These timing pulses are created using a technique called Constant Fraction Discrimination (CFD). Each of the sixteen channels in the IC contains a Nowlin circuit, leading-edge discriminator, zero-cross discriminator, and a one-shot circuit to generate the output.
The IC will support input pulse amplitudes between 15 mV and 1.5 V (both positive and negative), and input pulse rise times between 2 nsec and 192 nsec. The IC will feature a programmable output pulse width between 50 nsec and 500 nsec. The IC will have an average power dissipation of 220 mW and occupy an area of 2.4 x 3.5 mm. The variation (due to process and mismatch) in the trailing edge of the output timing pulse will be less than 5 nsec (for pulse width of 50 nsec). The assosciated jitter the output timing pulse is ≈20 psec (for the 50 nsec pulse width mode). Most importantly the output pulse firing time variation will be independent of the input amplitude, having a time walk of only 500 psec or less (for input pulse rise time constants of 2 nsec). The IC has been named CFD16C and the design presented is implemented in a 0.35 micron NWELL process.
|Commitee:||Noble, Brad, York, Timothy|
|School:||Southern Illinois University at Edwardsville|
|School Location:||United States -- Illinois|
|Source:||MAI 58/01M(E), Masters Abstracts International|
|Subjects:||Electrical engineering, Nuclear physics|
|Keywords:||Circuit, Constant, Discriminator, Fraction, Integrated, Radiation|
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