Dissertation/Thesis Abstract

III-V and 2D Devices: From MOSFETs to Steep-Slope Transistors
by Si, Mengwei, Ph.D., Purdue University, 2018, 148; 10838712
Abstract (Summary)

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-all-around tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2.

Indexing (document details)
Advisor: Ye, Peide D.
Commitee: Appenzeller, Joerg, Chen, Zhihong, Lundstrom, Mark S.
School: Purdue University
Department: Electrical and Computer Engineering
School Location: United States -- Indiana
Source: DAI-B 80/01(E), Dissertation Abstracts International
Subjects: Engineering, Electrical engineering
Keywords: III-V and 2D devices, MOSFETs, Steep-slope transistors
Publication Number: 10838712
ISBN: 9780438330696
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