The continuous improvement of modern electronics has been sustained by the scaling of silicon based MOSFETs over the last 4 decades. However, the frequency of the processors has been saturated since 2005 when the power dissipation in CPUs reached its cooling limit (100W/cm2). The thermionic emission in MOSFET limits the SS to 60 mV/dec, which prevents CMOS from further reducing the power consumption. Tunnel-FETs (TFETs) were proposed to solve this problem by removing thermal emission. Although, SS < 60 has been demonstrated experimentally in conventional TFETs, they suffer from low ON current, orders of magnitude lower than MOSFETs. Hence achieving high ON-current and performance requires novel device structures.
Low dimensional materials have unique features which can be used to solve the challenges of TFETs. In this work, several novel TFETs based on low dimensional materials (new channel material candidates such as Bilayer graphene, Black Phosphorous and interlayer TFETs based by stacking TMD materials) have been proposed to solve the low ON current issue. Their device performance and the scalability have been studied by means of atomistic quantum transport simulations.
|Advisor:||Klimeck, Gerhard, Manfra, Michael J.|
|Commitee:||Chen, Yong P., Chen, Zhihong, Datta, Supriyo, Peterson, John R.|
|Department:||Physics and Astronomy|
|School Location:||United States -- Indiana|
|Source:||DAI-B 79/11(E), Dissertation Abstracts International|
|Subjects:||Electrical engineering, Quantum physics, Nanotechnology|
|Keywords:||Device modeling, Emerging nanotechnology, Low dimensional materials, Low power transistor, Topological insulator, Transition metal dichalcogenide|
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