Dissertation/Thesis Abstract

Designing Time Efficient Real Time Hardware in the Loop Simulation Using Input Profile Temporal Compression
by Chatterjee, Sourindu, M.S., The Florida State University, 2017, 82; 10641144
Abstract (Summary)

The modern day smart grid technology relies heavily on data acquisition and analysis. A distributed controller governs smart microgrid functions with one or more renewable sources and smart controllable loads. This sort of intelligent, scalable system is the primary drive for the Energy Internet (EI). Hence, in modern-day power systems engineering to analyze, understand and make efficient system design choices that capture robustness and scalability, Hardware in the Loop (HIL) simulations are required. Real-Time Simulations (RTS) is the state of the art technology thrusting the capstone of innovation for this industry. As engineers, we can model, simulate and validate smart grids operations more rapidly, robustly and reliably using RTS. With enough smaller time step for the simulation, the boundary between the real and the simulated systems slowly vanishes. It also enables the system to be simulated as Controller Hardware in the Loop (CHIL) or Power Hardware in the Loop (PHIL) setups, evolving and imitating the real physical world. The HIL (Hardware in the Loop) setup also enables a real data source or sink to be in the system to form the loop of exchange between the simulated system and real-world hardware which is most often a control hardware. The implementation of such a setup is made possible at Center for Advanced Power Systems (CAPS), named as Hardware in the Loop Test-Bed (HIL-TB). This evaluation architecture provides a systematic solution to HIL simulations. Now the sampling time for real-world sensors is generally in the order of microseconds, enabling this collected data to emulate the cyber-physical domain accurately. Thus, the challenge previously was to address the throughput of real-world input data into the simulated system efficiently and correctly. The quality of the Design of Simulation (DoS) using the real world data in the form of Real Time Input Profile (RTIP), improves, affects the quality of response of the real-time cyber-physical system simulation. Thus great care needs to be taken to prepare, prune and project the RTIPs to improve and enhance the system performance evaluation index. To solve this problem, partially successful attempts have been made in the direction of machine learning by using methods like clustering and regression to characterize large input profiles or by breaking them into subsections using fixed length sliding window techniques. These classic methods then perform data analysis on those sub-pieces to distinguish among a variety of input profiles and assign an index. These sub-profiles or sections would be then loaded into the simulation as environmental input to represent the physical system in the HIL simulations. This traditional procedure is observed to be arbitrary because clustering algorithms and metrics for methods like regression or classification are user-defined and there exists no standard practice to deal with huge input profiles. There have also been confusions regarding the size of the sliding window to create subsections, subsection joining logic, etc. Thus, to address this issue, the primary focus of this study is to present a systematic, controlled, reliable procedure to explore, screen, crop large input profiles and then to compress the same by selecting sections with most relative importance using a modified version of “knapsack” dynamic programming algorithm. This compression primarily aims to shrink down the total simulation time without much loss of information. The latter part of this study focuses towards response driven performance evaluation of the HIL simulations. This is ensured by targeted compression of original input profile based on the certain requirement of the simulation. This approach ensures that the control algorithm (CHIL simulations) or any other system operator is driven in a specific direction in the simulation response space by effectively sampling the input parameters space. The fully automated HIL-TB evaluation framework aided with Input Profile Time Compression (IPTC) module delivers a fast-convergent validation for the performance evaluation with relatively similar system response. In this study, the IPTC module has been applied to seven load profiles to compress their temporal length by a third. The case study used for the simulation with these RTIPs is the Future Renewable Electric Energy Delivery and Management (FREEDM) IEEE seven node system. The test results show great coherence between the uncompressed and compressed response and validate the performance of the IPTC module applied to real-world HIL simulations. Thus, it can conclude that the functionality of the IPTC module is validated by the quality of simulation response gained out of the compressed simulation as compared to uncompressed simulation. (Abstract shortened by ProQuest.)

Indexing (document details)
Advisor: Faruque, Omar, Steurer, Mischa
Commitee: Li, Hui
School: The Florida State University
Department: Electrical and Computer Engineering
School Location: United States -- Florida
Source: MAI 57/04M(E), Masters Abstracts International
Subjects: Engineering, Electrical engineering
Keywords: Design of simulation, Hardware in the Loop simulaiton, Input profile compression, Real Time simulation, Time compression
Publication Number: 10641144
ISBN: 978-0-355-61969-0
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