Dissertation/Thesis Abstract

Design for Testability Support for Launch and Capture Power Reduction in an Integrated Circuit Based on Region Partition Testing
by Pulluru, Venkata Sahith, M.S., California State University, Long Beach, 2017, 37; 10638704
Abstract (Summary)

At-speed testing of very large scale integrated (VLSI) circuits aims for high-quality screening of the circuits by targeting performance-related faults. A compact test set with effective patterns creates lower testing costs. However, compact sets also increase switching activity during launch and capture operations, which frequently violate peak-power constraints, resulting in yield loss.

This project is focused on developing a Design for Testability (DFT) technique. DFT aims to enable the use of a set of patterns that are optimized for cost, quality, and reduced power consumption. DFT support enables a design partitioning approach, using a set of patterns to test the design regions one at a time. This reduces launch power and captures power. The DFT mechanisms used are launch-off shift and launch-off capture, which are used in a power gating manner. The use of these techniques decreased the power usage by 1micron watt, while increasing the area of the circuit.

Indexing (document details)
Advisor: Yeh, Hen-Guel Henry
Commitee: Aghnatios, Wajdi, Mozumdar, Mohammad
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 57/01M(E), Masters Abstracts International
Subjects: Engineering, Electrical engineering
Publication Number: 10638704
ISBN: 9780355488333
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