In order to meet the increasing demand of high data rate mobile broadband communication, newer standards increasingly employ spectrally efficient high order modulation schemes, which lead to large peak-to-average ratio (PAPR) of transmitted signals. To drive down the cost and form factor, a significant portion of the active circuitry in today’s commercial handsets is implemented in silicon CMOS technology – except for the power amplifier (PA). Silicon technology comes with low breakdown voltage, however, limiting the output power of the PA. Recent work has shown that series-connection of Si FETs (the “Stacked-FET” technique) can overcome the breakdown issue of silicon CMOS FETs to implement high power PAs. This can enable the use of scaled CMOS technology nodes which are optimized for digital logic circuits, to implement high performance PAs. The PAs, moreover, can make use of the digital circuits available to produce compact integrated circuits that are less dependent on microwave matching techniques than their counterparts. This work investigates the design and implementation of high output power, digitally-intensive PA CMOS architectures and their extensions for wireless transmitters that are highly efficient, even for signals with high peak-to-average ratio.
In the first part of this work, a digitally modulated PA (DPA) is implemented in polar architecture on 180 nm CMOS SOI technology. The amplitude modulation input signal is a 10-bit digital word controlling the number of active unit cells – each unit cell being a stacked FET PA. The DPA is also driven by a constant amplitude phase modulated (PM) signal centered at RF. The demonstrated DPA provides output power of 1.45 W at 900 MHz with drain efficiency of 65.9%. The power and efficiency are adequate for use in cellular handsets for 3G and 4G standards. The DPA can transmit WCDMA and LTE signals at 900 MHz and is functional from 800 MHz to 2.4 GHz with different matching networks. This DPA is a multi-band, multi-standard PA and is used as a building block for additional designs in this work.
The back-off efficiency enhancement of PA is critical to efficiently transmit signals of high PAPR from hand-sets. In the second part of the work, two identical DPAs are used to implement a digitally modulated Doherty power amplifier (DDPA). This part of the work investigates the challenges and develops the techniques for achieving strong efficiency peaking in output power back-off for CMOS Doherty PAs at microwave frequencies. The output combiner needed within the Doherty architecture is realized using surface-mount components on a printed circuit board (PCB). Digital AM signals to both DPAs are independently provided as inputs. The phase difference between RF PM inputs of main and peaking DPAs can also be varied. The peak output power of CMOS DDPA at 900 MHz is >2 W (highest reported in the literature) with drain efficiency of 55.5%, while at 6 dB back-off the drain efficiency is 52.6%. The back-off efficiency and its improvement relative to class-B is highest reported in the literature for any CMOS Doherty implementation. The DDPA is demonstrated to transmit 5 MHz 64-QAM OFDM signal with very good linearity of ACPR better than -35.9 dB and EVM of 3.8%.
For applications like femto-cell base-stations, where the power needed is large, technologies like Gallium Nitride (GaN) work better than silicon because of superior voltage handling. The challenge here lies in efficiently driving the GaN FETs. The DPA developed in this work can provide large enough voltage to directly drive the input of GaN FET, thanks to the use of FET stacking. A novel architecture is demonstrated in which the CMOS DPA drives the GaN FET, which is connected as a common gate stage, with no inter-stage matching. The GaN FET in turn drives a 50 Ω load directly. The absence of any impedance matching network (with its associated bandwidth limitation) makes this PA wideband. Key design aspects of this architecture, including bandwidth limitation caused by circuit parasitics, are discussed in this work. A digitally controlled PA with a combination of CMOS and GaN (Mitsubishi Electric 0.75 μm process) is demonstrated. The CMOS-GaN PA operates over a 2.4:1 frequency range for 1dB output power variation (500 MHz to 1.2 GHz); output power varies from 2.4 W to 3 W with efficiency between 48% to 74%. This PA is demonstrated to transmit 5 MHz, 64 QAM signal at various frequencies. These characteristics make this amplifier a candidate for application in femtocells and microcells.
|Commitee:||Buckwalter, James, Cauwenberghs, Gert, Hodgkiss, William, Mercier, Patrick|
|School:||University of California, San Diego|
|Department:||Electrical Engineering (Electronic Circuits and Systems)|
|School Location:||United States -- California|
|Source:||DAI-B 78/11(E), Dissertation Abstracts International|
|Keywords:||CMOS power amplifier|
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