This project report presents a fast-acquisition all-digital delay-locked loop (ADDLL) using a starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). The SBP effectively eliminates the harmonic lock and the false lock. The ADDLL design allows wide clock frequency range operation. The algorithm and the digital circuit are digitally simulated and the performance and the advantage over the Conventional-SAR are shown.
|Commitee:||Mozumdar, Mohammad, Wagdy, Mahmoud, Yeh, Henry|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 56/03M(E), Masters Abstracts International|
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