Dissertation/Thesis Abstract

A fast-acquisition all-digital delay-locked loop using a starting-bit prediction algorithm for the successiveapproximation register
by Sachdeva, Arjun, M.S., California State University, Long Beach, 2016, 46; 10252211
Abstract (Summary)

This project report presents a fast-acquisition all-digital delay-locked loop (ADDLL) using a starting-bit prediction algorithm for the successive-approximation register (SBP-SAR). The SBP effectively eliminates the harmonic lock and the false lock. The ADDLL design allows wide clock frequency range operation. The algorithm and the digital circuit are digitally simulated and the performance and the advantage over the Conventional-SAR are shown.

Indexing (document details)
Advisor: Wagdy, Mahmoud
Commitee: Mozumdar, Mohammad, Wagdy, Mahmoud, Yeh, Henry
School: California State University, Long Beach
Department: Electrical Engineering
School Location: United States -- California
Source: MAI 56/03M(E), Masters Abstracts International
Source Type: DISSERTATION
Subjects: Electrical engineering
Keywords:
Publication Number: 10252211
ISBN: 978-1-369-51197-0
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