The objective of this thesis is to compute the Misadjustment of Adaptive Predictors and to implement their fixed-point design on Xilinx Vivado for a behavioral simulation of the Prediction Gain. In the first part of this thesis, the Misadjustment is mathematically calculated for Adaptive Predictors of different tap-weights. These Adaptive Predictors include Least Mean Square (LMS), Forward-Backward LMS (FBLMS), Cascaded LMS (CLMS), and Cascaded Forward-Backward LMS (CFBLMS) for 2, 4, and 6 tap-weights. In the second part of this thesis, the 6-Tap design of all the four predictors is programmed in Verilog Hardware Description Language (HDL) using MATLAB’s HDL Coder tool and run on the Xilinx Vivado platform for comparing behavioral simulations of the Prediction Gain with that obtained on MATLAB. An alternative method for the Prediction Gain comparison is accomplished by instantiating Xilinx Analog-to-Digital Converter (XADC) block available on 7-series Field-Programmable Gate Array (FPGA) boards as a means to introduce the input signals as voltage values.
Misadjustment is determined for 2, 4, and 6 tap-weights on all four Adaptive Predictors previously mentioned for input signals such as a sinusoid of frequency 0.1Hz contaminated with White Gaussian Noise (WGN), a second-order Auto-Regressive (AR) process, and a speech signal at 8Kbps. The results in every case reveal that FBLMS and CFBLMS show better performance, in terms of Misadjustment, when compared to LMS and CLMS Adaptive Predictors, respectively. Also, irrespective of the input signals, only the 2-Tap cascaded Adaptive Predictors such as CFBLMS and CLMS exhibit lower Misadjustment than the 2-Tap non-cascaded FBLMS and LMS predictors. And, in the case of the second-order AR process input, if AR parameters are chosen so that the eigenvalue spread is sufficiently large, then the performance of 2-Tap, 4-Tap, and 6-Tap CFBLMS and CFLMS predictors have a lower Misadjustment than that of FBLMS and LMS predictors.
The Prediction Gain calculations for the speech signal input on all the four predictors reveal that the 6-Tap CFBLMS and CLMS Adaptive Predictors show much higher gains compared to 6-Tap FBLMS and LMS Adaptive Predictors. All four 6-Tap predictors, after quantization of tap-weights to reduced number of bits for a fixed-point design, are HDL programmed on Xilinx Vivado. The behavioral simulation for Prediction Gain obtained using both the methods described reveal that the result is nearly the same as the Prediction Gain value obtained using a MATLAB simulation thereby validating the fitness of the design for FPGA implementation. Also, instantiating the XADC block for introducing input voltages, rather than hardcoding input voltages as binary-coded-decimals into Testbench, gives the leeway to feed different sets of input signals directly as voltage parameters.
|Commitee:||Tsang, Chit-Sang, Wagdy, Mahmoud|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 56/02M(E), Masters Abstracts International|
|Keywords:||Artix-7, Cascaded and non-cascaded linear adaptive predictors, Least Mean Square (LMS) algorithm, Misadjustment, Prediction Gain, Xilinx Vivado|
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