The current project presents the architecture of an efficient anti-collision technique for the identification of Class 0 RFID UHF tags. The architecture consists of two RCEAT (Reliable Cost Effective Anti-collision Technique) subsystems: PreRCEAT and PostRCEAT. The PreRCEAT subsystem is used to detect if the incoming messages have any errors in them. PreRCEAT applies a cyclic redundancy check to find an error in the ID (Identification) tag. The ID of the error-free packet will be sent to PostRCEAT, which uses a fast search lookup table to identify the incoming tag. It sends the output serially from the smallest ID to the largest ID. The system is designed using Verilog and simulated using Xilinx ISE. Simulation results show that the proposed architecture requires smaller cell area, and has lower power consumption compared to the popular Tree algorithm. The proposed system uses fewer logic gates, which minimize the implementation and operating cost.
|Commitee:||Tran, Boi, Yeh, Hen-Geul|
|School:||California State University, Long Beach|
|School Location:||United States -- California|
|Source:||MAI 56/02M(E), Masters Abstracts International|
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