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Dissertation/Thesis Abstract

Implementation and evaluation of a double-adjacent error correcting code in an FPGA
by Malley, Brian J., M.S., California State University, Long Beach, 2016, 80; 10196051
Abstract (Summary)

Soft errors caused by radiation are a common problem in spaceflight due to the intense radiation environment of space. Single Error Correction (SEC) Error Correcting Codes (ECCs) are a traditional approach to solve this problem, but with the increasing density of IC architectures, multiple-bit errors are becoming more common. Double Error Correction (DEC) ECCs are costly, but codes between DEC and SEC, which take advantage of the spatial locality of bit errors and correct only adjacent double-bit errors, have been found by others. In this thesis, one of those codes is implemented and evaluated on a Spartan-6 FPGA. The results of several error trials are presented herein, along with implementation details, including the source code. Tables of the trial results and the specific FPGA resources used are also presented. The implementation is found to have a non-negligible area cost, but low latency cost. Another implementation of this same ECC with potentially low area but high latency is also described. When errors well beyond the ECC’s capability, such as multiple single-bit errors, or four-bit errors, are injected, around 30% of the time the code erroneously claims to have fixed an error. In these same circumstances, however, the ECC implementation hardly ever (0.2%) claims that no error has occurred. This suggests that a simple extension to a more conservative ECC which flushes data on any error could be used in situations with error rates that surpass the ECC’s capability to maintain data integrity.

Indexing (document details)
Advisor: Englert, Burkhard
Commitee: Aliasgari, Mehrdad, Tramel, John
School: California State University, Long Beach
Department: Computer Engineering and Computer Science
School Location: United States -- California
Source: MAI 56/02M(E), Masters Abstracts International
Subjects: Computer Engineering
Keywords: Error correcting codes, FPGA, Field programmable gate arrays, Hamming codes, Hardware, Parity check codes
Publication Number: 10196051
ISBN: 978-1-369-33929-1
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